Advanced Diamond Technologies, Inc.
Ultrananocrystalline Diamond Wafers

For decades designers and engineers have sought to harness the unsurpassed properties of diamond for MEMS and electronic devices. Despite the keen interest, diamond has been notoriously difficult to work with, is prohibitively expensive for mainstream applications and there hasn’t been a reliable supply. Enter UNCD Wafers.

UNCD Wafers from Advanced Diamond Technologies, Inc. suddenly make diamond affordable and accessible for MEMS and IC applications. UNCD (for ultrananocrystalline diamond) is the only phase-pure nanocrystalline diamond film in the world and is comprised of diamond grains that are as small as 5 nm in diameter - a billion-fold smaller in volume than in traditional diamond films. UNCD differs from other nanocrystalline diamond films in that other films are comprised of graphitically-bonded material intermixed with crystalline diamond grains. UNCD, in contrast, has no amorphous or graphitic phases. UNCD Wafers capture the hardness, modulus and other extreme properties of natural diamond but are also smooth and have very low internal stresses making them suitable for a variety of applications. UNCD Wafers meet basic foundry level standards including wafer bow, particle count and thickness uniformity.

Most MEMS devices are based on silicon due to the availability of microfabrication techniques developed for the integrated circuits industry. Diamond has unsurpassed bulk and surface properties that exceed those of any other material, and UNCD Wafers are the base material for MEMS device fabrication. The availability of 200 mm UNCD Wafers and standard microfabrication techniques for processing (reactive ion etching) provide for the ability to manufacture diamond devices in a standard foundry environment.

UNCD Wafers are a critical enabling technology because they provide the mechanism for designers to begin building diamond devices today.

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Alchimer
eG ViaCoat material for TSV metallisation

eG ViaCoat is the enabling material for Alchimer's breakthrough proprietary electrografting process. eG ViaCoat has been developed specifically for the metallisation of high aspect ratio through-silicon vias (TSVs) used in advanced 3D packaging applications.

eG ViaCoat is a mild acidic aqueous copper electrolyte solution that enables the deposition of ultra thin, homogeneous, uniform, adherent and conformal layers. The material is specifically formulated for creation of copper seed layers on widely adopted barrier layers (including, but not limited to, PVD, CVD and ALD deposited Ta, TaN, Ti, TiN, WN, Ru and bi-layers). Electrografting is a wet electrochemical process based on specific organic precursors enabling the initiation and growth of thin films on conducting and semiconducting surfaces. The process can produce conformal, thin, uniform and adherent copper seed layers, even on resistive barriers. It works by 'grafting' molecular precursors to a variety of conductive materials, through creating covalent bonds between the materials.

Because the size of the precursors being introduced is in the order of 0.5nm, it provides a method of depositing material at the scale required for leading edge process nodes, both today and in the future. The substrate is placed in contact with a wet solution and the process operates by applying a small electric current: due to the very nature of the molecular precursors and of the reaction mechanisms they can undergo, unusually small amounts of current - of the order of 1 to 10 µA/cm² - are enough to trigger the process uniformly at any point of the surface of the substrate. This is called the electro-initiation step, which involves electronic transfer from the surface to the adsorbed precursors at chemical bond distance.

Once the surface is "seeded" with adsorbed activated moieties, the same precursors can undergo alternative chemical reaction paths which lead to the formation of the desired layers: while the process is controlled by the electro-initiation step, subsequent steps immediately following the electro-initiation may involve purely chemical reactions depending on the nature of the molecular precursor. In any case, the electro-initiated nucleation secures the growth of the film in a conformal and uniform manner. Through controlling just the current, Alchimer is able to demonstrate the deposition of ultra thin films of less than 10nm, with high uniformity across surfaces over a broad range of substrate resistivities.

One of the first applications of electrografting technology is copper seed layers in TSV metallisation. eG ViaCoat has the unique ability to enable ultra-thin and conformal copper seed layer deposition in the 50 to 500nm range, a major roadblock to 3D packaging adoption due to the dry vacuum processes in use for the past 40 years. This process can easily be implemented using industry-standard copper electroplating equipment, removing any requirement for additional capital expenditure.

PVD (physical vapor deposition) processes have already reached their limitations in terms of producing continuous layers for through silicon vias with aspect ratios of 3:1 and above. In practice, this is a major roadblock to the adoption of advanced 3D packaging. Alchimer's electrografting process using eG ViaCoat demonstrates conformal sidewall and bottom coverage even on highly scalloped TSV etch profiles, and at aggressive TSV aspect ratios. Reliable metallisation of TSVs with aspect ratios of 13:1 is now possible.

eG ViaCoat enables significant reductions in cost of ownership (CoO) compared to dry vacuum processes. For example, for 10:1 aspect ratio TSVs, the CoO of Alchimer's electrografting process is 85% less than that of a traditional PVD process. The cost advantage increases further at higher aspect ratios and electrografting can be applied using industry-standard copper electroplating equipment, eliminating new capital expenditure.

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Honeywell Electronic Materials
Reusable Thermal Interface Materials

This material provides outstanding, repeatable thermal performance over many thousands of test cycles. The material is used during the semiconductor burn-in testing process, which is a critical step in verifying that newly created microchips meet lifetime and performance requirements.

During the burn-in process, sample chips are subjected to extreme heat. Burn-in materials are used to transfer that heat to the chip for the test. Traditional materials that have been used for this application provide good thermal performance, but their use is limited to a single cycle and a residue is typically left behind that must be cleaned before the next test.

Honeywell's material eliminates the cleaning step and, since it can be used repeatedly, reduces material usage. The new material also has superior performance to alternative multi-use thermal interface materials used for burn-in. Besides the described application as a burn-in material, Honeywell's material can also be used in a broad spectrum of processes as a thermal interface material (TIM) for thermal modules or assembled packages.

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SILECS, INC.
New use of spin-on dielectric materials to enable new generation of CMOS sensors

Increasing the performance requirements in CMOS image sensors (CIS) for digital cameras is driving a need for improvements in both the optical portion of CIS devices and the durability of the camera module assembly.

Enabling materials innovator, Silecs, has developed two novel uses of Spin-on Dielectric (SOD) materials to accomplish both of these objectives. Each of the new approaches uses SOD in the construction of the optical stack, in contrast to the organic photo resist-like materials conventionally employed. In the first method, a vertical light guide (VLG) structure is formed in the device backend and filled with high refractive index SOD (RI=1.65 @ 633nm) to improve optical performance. The second method employs a low refractive index SOD (RI~1.28 @633nm) topcoat, which enables easier micro lens engineering and optimization, and also offers the advantage of protecting the organic micro lens with a glass-like layer.

Silecs has applied the VLG technique to successfully integrate a VLG structure in a 0.18um and below image sensor structure and compatible with both Al and Cu backend. Unlike conventional approaches, the resulting optical stack is not diffraction-limited. Excellent planarity above the optical elements was achieved, eliminating the potential need for CMP, and dark current performance was not compromised.

Silecs has likewise demonstrated the effectiveness of the second technique, using low RI SC500 as a topcoat. The glass-like behaviour of this SOD material offers the advantage of micro lens protection during sawing and improves epoxy base-like packaging compatibility. The SOD was engineered to enable excellent planarity or conformality above micro lens array with superior film quality. The use of a low refractive index topcoat enables focal lengths in the intermediate range (between backend without topcoat and backend with a common organic topcoat).

Further, the technique introduces an extra degree of freedom in the design of optical system focal length through control of the SOD bake conditions. When the focal length is kept the same for an existing integration scheme with or without topcoat, the same optical performance is obtained. This is achieved by adjustment of micro lens height for each case. Again, there is no degradation in dark current performance.

The two integration schemes (VLG and lens topcoat) are complementary, and when used in combination, will help enable a new generation of more efficient, sensitive and reliable CMOS sensors that have a smaller footprint. The work was conducted at Silecs' state-of-the-art production facility in Espoo, Finland. Here, Silecs' advanced enabling materials are developed and manufactured in semiconductor-like clean-room conditions, mirroring the production environments of the company's microelectronics manufacturing customers.

Process represents a unique new way to use spin-on dielectric materials; process resulted in significant performance improvements; process enables a new generation of more efficient, sensitive and reliable CMOS sensors with a smaller footprint. Work was conducted with leading customer in Silecs' state-of-the-art mfg facility in Espoo, Finland with production conditions that mirror microelectronics\' clean-room environments. Silecs is a thriving emerging player in the highly competitive electronic materials industry.

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DuPont/EKC Technology
Copper/low-k post-etch residue remover

The CuSolve EKC520 copper/low-k post-etch residue remover is a rapid, single-wafer cleaning solution for copper interconnect post-etch residue and copper oxide removal. It effectively removes residues from via first/trench last and trench first/via last structures; works with single and dual damascene processes; and is compactible with copper, barrier, and low-k films, and all single-wafers tools. The product reportedly meets particle performance requirements for advanced technologies, in water soluble, and can be disposed of in aqueous disposal drains. No post-clean rinse other than water is required. RC delay reductions of up to 7% have reportedly been achieved at a major copper foundry. DI water savings of >1.2 million gallons/month, or >15.2 million gallons/year can be realized using an EKC520 process for a wafer fab running single-wafer tools on 65nm devices (10 levels of metal, 2 cleans per level).

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Entegris
Ultrapak Edge Guard wafer shipping box

The Ultrapak Edge Guard 200mm wafer shipping box is said to reduce edge contamination, with 50% or more reduction in particle contamination from edge contact. This is expected to prevent particle-induced device defects during circuit fabrication. Designed for re-use, the shippers have horizontal and vertical robotic pick-up flanges on the cassette, while centre notch track alignment and H-bar features ensure accurate equipment interoperability.

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Ferro Electronic Material Systems
Self-stopping CMP slurry

The SureStop 8500 self-stopping chemical mechanical planarization slurry for inner layer dielectric materials provides a reported planarization efficiency of >95% with an increased over-polish window and eliminates the need for endpoint detection. The 8500 can be used to simplify planarization processes that employ reverse-mask etchback steps. This slurry contains chemistries that exhibit topography-dependent polishing behaviour that coat the wafer surface to automatically stop polishing when the topography has been removed. The slurry removes oxide topography (“Up” oxide) of up to 20,000A in step height with very little removal of the oxide at the bottom of trenches (“Down” oxide) for high planarization efficiencies throughout the polish. SureStop 8500 provides step height removal of >5000A/min and blanket removal rates of <300A/min.

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Okmetic Oyj
G-SOI - gettered SOI substrates for integrated MEMS and CMOS processes

Okmetic has developed a new thick BSOI product with built-in gettering properties (G-SOI). The wafer is designed for integrated MEMS and CMOS processes. The gettering effect is achieved by a buried polysilicon layer between the active layer and the buried oxide of a BSOI structure.

The push towards G-SOI product development came from a gate oxide integrity problem that was encountered when CMOS processes were implemented on standard thick BSOI wafers. It took the form of midfield breakdown sites while testing the gate oxide breakdown voltage, for example. The occurrence of gate oxide failure was traced back to the starting material, and in particular to the metal impurities in the active layer. The active layer has no gettering sites, and the buried oxide in a BSOI structure prevents diffusion of most transition metal impurities out of the active region into the bulk or the back surface of the wafer where the gettering sites are normally formed. To find a solution that is layout-independent, a thin polysilicon layer was added between the active silicon layer and the buried oxide layer.

Gettering efficiency was estimated based on DLTS measurement of iron (Fe) concentration in the active region after intentional contamination of BSOI wafers. A thin polysilicon layer in a BSOI wafer reduces the Fe concentration below the detection limit 1E+11 at/cm3, compared to 1.9E+13 at/cm3 in a standard BSOI wafer, implying gettering efficiency > 99%. The result is independent of the polysilicon film thickness from 0.2 m to 1.0 m. A high temperature process simulation was carried out based on a process cycle with 24 h at 1000°C, and a maximum temperature 1150°C for 4 h. The gettering efficiency analyzed after the high temperature processing of wafers was > 97%.

The buried polysilicon layer solves the gettering problem for metal impurities in bonded SOI wafers for integrated MEMS and CMOS processes where SOI is required for the realisation of the sensor element. Testing of wafers in CMOS processes show clearly better gate oxide integrity than in standard BSOI wafers, and in fact it is as good as in conventional bulk silicon wafers.

The wafer is designed for integrated MEMS and CMOS processes where the SOI is required for realisation of the sensor element. It can also be used in bipolar/BiCMOS applications.

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Camtek Intelligent Imaging Ltd.
Falcon line of automated wafer inspection & metrology systems

Camtek designs, develops, manufactures and markets technologically advanced, cost-effective systems and related software products that are used to enhance processes and yields. Camtek provides intelligent, automated optical inspection systems (AOI) to the Semiconductor Manufacturing and Packaging, IC Substrates, and Printed Circuit Board (PCB) industries. The company addresses the specific needs of each industry with dedicated solutions, based on a common core of intelligent imaging technologies.

The Falcon Family Advanced packaging of semiconductor devices depends on known-good-die to ensure high production yields and reliable device performance. Defects in the active die area or on interconnect pads, as well as deviations inbump dimensions and placement, may lead to device failure. Built upon over 20 years of experience in developing automated optical inspection (AOI) systems, the Falcon family addresses wafer-level inspection needs at production rates . The systems help semiconductor and MEMS manufacturers, bumping service providers, packaging foundries and test houses monitor their production processes and enhance yield. The Falcon systems measure and detect surface defects, as well as probe mark damage to bond pads. They measure deviations in solder and gold bump height, shape, size and placement. The systems inspect at pre-test, post-test, and post-dicing stages to check that dice are free of mechanical damage or contamination and that bond pads and flip-chip bumps can support a reliable interconnect. Camtek's modular, software-based architecture ensures flexible adaptation to each of our customer's individual needs.

Integrating 2D and 3D metrology and inspection systems on the same platform enables the Falcon to analyze bump co planarity or report statistical data for process monitoring.

An on-line statistical process control (SPC) package outputs relevant charts to assist quality assurance engineers identify root causes of defects, thus reducing process variations and enhancing production yields.

Falcon's high productivity results from its advanced electro-optics and massive computing power while its superb detection ability comes from its expansive set of sophisticated detection engines.

Performance, Responsiveness and Support: Performance:
- the Falcon family offers modular and software-intensive architecture, which enables flexible adaptation to customer-specific road maps and high versatility for standard and non-standard applications. This combination of performance and flexibility with ease of operation and reliability delivers to customers the optimal capital investment in inspection equipment.

Responsiveness:
The software-based, modular architecture of Falcon's systems enables addressing unique customer requirements with a high degree of customization, as well as providing an easy and cost-effective field upgrade package for existing equipment.

Support:
Camtek appreciates the value of strong field support at close proximity to the customer manufacturing plant. Therefore Camtek has established a world-class, customer support infrastructure. Organized in eight subsidiaries in the US, Europe, Japan, China, Hong Kong, Taiwan, Korea and Singapore, Camtek provides local service, spare parts, training, demo and sales services to its customers wherever they are located.

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Carl Zeiss SMT - SMS Division
E-beam Mask Repair System MeRiT MG 45

Carl Zeiss has developed a unique mask repair system based on electron-beam technology called MeRiT MG 45. This system overcomes the physical limits of almost all currently existing mask repair technologies e.g. focus ion beam, nanomachining or laser repair. With the continuing decrease of feature sizes on photomasks, the rising costs and the necessity to manufacture 100% error free reticle it is essential to have one industrial solution to perform reliable repairs on photomasks.

MeRiT MG 45 is the only viable solution meeting the challenging requirements for mask repair at the 45 nm node. The system allows opaque and clear defect repair in one platform. Thereby electron beam induced chemical gas phase reaction in ultra high vacuum for either selective etching or deposition of the respective mask materials.

Compared with previous technologies the MeRiT MG 45 uses a high resolution low energetic electron beam instead of ions or tips. This principle outperforms all other concepts. The process is only limited by the diameter of the electronic beam, which can in principle be downsized to sub nm range. Furthermore, the use of electron beams prevents radiation damage on the photomask.

The MeRiT MG 45 has an automated die to reference and die to database defect recognition. This allows a high level of automation to ensure reproducibility and efficiency. The repair process itself is partially automated as well. Depending on the material automated recipes chooses the appropriate precursor gases, either a local etch or a local deposition. Even defects which require complex combination of different etch or deposition steps can be repaired.

Photomasks typically have a surface which charges up when using electron or ion beams. The MeRiT MG 45 has a proprietary charge compensation technique to mitigate electron beam interaction with surface charging. A combination of annular secondary electron detector and annular energy selective backscattered electron detector, is mounted in the column. These detectors are specifically optimised for the purpose of high definition imaging. Furthermore they are used for ultimate precision and automated end-pointing of repair processes. As a result the MeRiT MG 45 system delivers the highest first pass yield of any repair tool known to the industry.

Employing electron-beam technology overcomes the physical limits of existing mask repair technologies and has the following strong advantages:

• Superior resolution and accuracy for all known kinds of repair
• Repair process causes no transmission loss and no contamination
• No mask structure modification during imaging allowing degradation-free review cycles
• E-beam induced chemical reactions without any sputter contribution
• Automated repair identification
• Automated repair endpointing
• High imaging signal-to-noise ratio allows excellent defect review
• Multi-node capability down to 45nm node and in some respects even below
• All-in-one-tool minimising processing overhead

MeRiT MG 45 enables the repair of all kinds of photomasks including phase shifting masks with tuneable phase and transmission matching. It is also suitable for next generation lithography such as NIL or EUV.

MeRiT MG 45 is the only photomask repair technology for 45nm node Enables manufacturing of advanced photomasks ZEISS photomask repair system led to paradigm shift in mask repair technology Optimizes yield of high-end photomask manufacturers Only concept which is applicable for the 45 nm node and down scalable to the 22 nm node (and maybe below).

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Metryx Ltd
The Metryx Mentor

The Metryx Mentor provides a new generation of metrology tool based on innovative mass metrology for materials development and SPC / APC. The Mentor is designed to monitor changes in process performance, and quickly determine whether device manufacturers’ process steps are operating correctly by measuring the mass change of any product wafer through a process step. Simple statistical analysis of the measurement data enables the tool to reliably and accurately identify process changes after deposition, wet or dry etch, or CMP Processing. The tool achieves measurements down to the equivalent of one Angstrom of material thickness over an entire wafer.

In simple terms, by measuring the change in the wafer mass, variations can be detected on product wafers, and problems in the process can be identified very early on - saving valuable time, money and wafers. The technology is extremely reliable and cost effective, improving yield and reducing scrap with a low cost of ownership. The Mentor’s measurement technique is effective for all substrates, wafer sizes, wafer types and materials. It is non-destructive and compatible with product, test and blanket wafers.

The Mentor provides a family of reliable, low cost, high throughput, fully automatic mass determination tools with atomic layer repeatability for high volume manufacturing environments. Capable of throughputs of 60 wafers per hour, the Mentor tool has a small footprint of only 2 m² and provides nanotechnology mass measurement of product, test and blanket wafers independent of substrate size or material.

• Metryx has fully automated 300mm in-line metrology systems running volume production, and has been endorsed by major 200 mm and 300 mm fabs worldwide.
• Technology used is protected by international patents.
• Product designs comply with SEMI standards and industry standard components, and software protocols are used throughout.
• Multiple unit installations, running critical applications in fully automated production environments, have proven to be both reliable and cost effective.
• Key advantages include high throughput, low cost of ownership, independent of substrate, wafer size, wafer type and material.
• The measurement technique is also non-destructive and compatible with product, test and blanket wafers.

The Mentor is equipped with a standard equipment front end module (EFEM) housing an atmospheric robot within a mini-environment. The wafer handling capabilities of the tool rely on two front opening unified pods (FOUPs) located side by side at the front of the system. The tool is able to pre-identify the FOUP adaptors to achieve seamless handling.

The Mentor can also be configured to serve as a bridge tool in mixed wafer fab environments where 200 mm and 300 mm wafers are continually interchanged. For use as a bridge tool, one of the tool’s load-ports can be configured for 200 mm (either open cassette or SMIF) operation while the other remains at 300 mm.

If the semiconductor manufacturing process is made up of a series of steps that see material deposited and material etched or polished away, it follows that each of these steps will have an impact on the mass of any given wafer. That impact is an increase or decrease in the wafer’s mass. It then follows that by monitoring mass, we can accurately determine whether the deposition, etch or planarization process is working as it should or not. In theory, it sounds simple; it is a common sense approach to a very technical problem. In reality, Metryx has delivered a complex system that can determine process stability and performance more effectively and more cost-efficiently than any other solution on the market today.

Based on an ancient form of measurement, Metryx's Mentor technology is revolutionary in terms of the value it offers semiconductor manufacturers as an inline, on-product metrology tool. Simply put, being able to identify a process variation at the nanotech level as soon as it happens saves manufacturers a significant amount of money by reducing scrap and rework. As an inline tool, the Mentor offers a fast and reliable method to ensure a process is running correctly without having to wait for an offline tool, or losing a wafer to test. Further, the Mentor’s ability to be implemented following virtually any process step makes it one of the most versatile metrology tools on the market that is not restricted to use after selected process steps. As such, the Mentor can be incorporated in-line in virtually any area of the fab.

Over and above the technical advantages the Mentor brings to semiconductor manufacturing, it has been demonstrated to be commercially viable, rapidly increasing its adoption over the past 5 years, with follow-on orders accounting for fifty percent of its sales. In other words, once manufacturers use the Mentor in a manufacturing environment its value becomes quickly evident, leading to additional orders. The Mentor has proven its capabilities for advanced semiconductor manufacturing, as evidenced by its adoption in multiple leading 200 mm and 300 mm semiconductor manufacturing lines located around the world.

Metyrx are doubling revenues on an annual basis as our technology becomes more widely accepted in the IC manufacturing process. The basis of this growth is our Mentor technology and the capability that this technology provides our customers.

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Qcept Technologies
ChemetriQ 3000

The ChemetriQ 3000 provides rapid, full-wafer, inline detection of non-visual defects (NVDs). NVDs include both organic and inorganic residues, metallic contaminants, process-induced charge defects, as well as watermarks and other non-visual residue defects.

The ChemetriQ 3000 accomplishes this by employing an innovative, non-contact, non-destructive technology that detects work function variations on the surface of semiconductor wafers. These variations, which mark the presence of NVDs, are converted into image files using on-board software that can be easily ported to a fab's existing analytical tools for enhanced defect classification. The ChemetriQ 3000 is sensitive to 5E9 atoms/cm2 (one atom out of 200,000 per square centimetre), which exceeds the requirements outlined in the ITRS Roadmap for metallic contamination detection down to the 22-nm node.

Leveraging the ChemetriQ 3000, semiconductor manufacturers can reduce their yield loss through improved process monitoring, and achieve faster yield ramps through accelerated process optimization. For example, the

ChemetriQ 3000 detects NVDs non-destructively in four minutes compared to up to six hours with destructive analytical methods, making it ideally suited for inline process monitoring.

The ChemetriQ 3000 is highly complementary to today's existing optical inspection technologies, filling the inspection gap that exists today for a full-wafer, production solution that enables detection of NVDs.

As the missing link in moving the detection of NVDs to a highly automated inline process, the ChemetriQ 3000 enables chipmakers to broaden and expand their existing solution set to solve their NVD yield challenges.

As IC manufacturers integrate more new materials and processes into their manufacturing lines to improve the performance of their devices, process quality becomes ever-more critical to device yields. This is especially true with wafer cleaning and surface preparation, which are the most repeated process steps in the fab and among the most frequent sources of yield loss. The introduction of new materials has further narrowed the slim process margins associated with these processes, giving rise to NVDs.

In leading-edge semiconductor fabs, NVDs now account for as much as 30 percent of all defects. Since NVDs do not scatter light, they are undetectable by optical inspection systems. According to the latest edition of the ITRS Roadmap, the rapid sourcing of non-visual defects will become increasingly challenging-driving the need for affordable inspection techniques that go beyond optical microscopy and offer high resolution without sacrificing throughput. The ChemetriQ 3000 platform is the only inline wafer inspection solution that can detect NVDs.

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Sela
MC600i

The Sela MC600i achieves a fully automatic, reliable and rapid cross sectioning of wafer segments and dies. It is used to prepare samples, either for the analysis of defects, or to validate process steps. The area of interest is located and cross sectioned. Without further processing, the sample is ready for analysis on an SEM. It has dedicated software that enables automatic mapping and navigation to targets. It also features automatic off-loading for immediate inspection. Sela's MC600i has reduced the time required to locate and cross-section areas of interest from hours to less than 10 minutes with a fully automated process. The process is automated, and only basic training is required to use the system to obtain samples with no artifacts. Other than liquid nitrogen (usage is optional), absolutely no chemicals (not even water) are required by the process.

The microcleaving technology is patented and there are no systems available that cleave samples. Other methods used to produce samples involve sawing, grinding, polishing, or FIB milling - each requiring multiple machines and in-process inspections as the process approaches the target area. These are manual processes that require significant experience to achieve the desired results. Unlike micro cleaving, these methods create only one workable sample - one side of the sample is destroyed by the process. The MC600i produces two samples (each a mirror image of the other) for analysis. Worker safety is also improved because manual breaking of wafer segments is eliminated. Other benefits of the MC600i include high throughput (9 min/sample) and accuracy (less than 0.3 micron), superior cross-section quality, and it significantly reduces the diagnostic cycle for both failure analysis and process monitoring. Specification capabilities include cleaving of smaller wafer segments and dies as close of 0.5mm to a sample edge. High throughput (9 min/sample) High accuracy (less than 0.3 micron) Reduces time to look and cross-section the wafer(s) Able to get two samples for analysis from one cleave Artifact-free Chemical usage is not required Back to top

FEI Company
Helios NanoLab 400S

The Helios NanoLab series is the world's most advanced DualBeam platform for sample preparation, imaging and analysis in semiconductor failure analysis, process development and process control laboratories. All Helios NanoLab systems combine the innovative Elstar electron column for high-resolution, high-contrast imaging with the high-performance Sidewinder ion column for fast, precise cross sectioning. The advanced system design optimizes the column configuration to provide the best combined performance available in any dual beam (FIB/SEM) system. The Helios NanoLab 400S is optimized for high throughput, high-resolution S/TEM sample preparation, imaging and analysis. Its exclusive FlipStage and in-situ STEM detector can flip from sample preparation to STEM imaging in seconds without breaking vacuum or exposing the sample to the environment.

The FilpStage mounts on a five-axis motorized stage that accommodates samples up to 80 mm in diameter with full coverage and industry-leading repeatability. Samples up to 100 mm can be introduced through the load lock for optimal throughput. Larger samples may be introduced through the chamber door. Elstar Electron Column The innovative Elstar electron column, newly introduced in the Helios NanoLab series, provides the foundation of the systems' unprecedented high-resolution imaging capability. Helios NanoLab systems are capable of 0.8 nm STEM resolution. SEM resolution is equally impressive with 0.9 nm at optimal working distance and 1.0 nm at the DualBeam coincident point. Imaging performance is further enhanced by advanced scanning and through-the-lens signal detection systems that provide dramatic improvements in contrast and signal-to-noise ratio. Double magnetic shielding increases the systems' immunity to environmental fields. Constant power lens technology eliminates thermal instabilities caused by routine changes in lens power. Sidewinder Ion Column The Sidewinder ion column combines high-resolution with exceptional low voltage performance. Not only does it enable excellent ion image resolution (5 nm @ 30 kV, coincident WD), it also provides the most precise ion milling, helping to insure that valuable defect information is not destroyed by the cross sectioning operation. A full range of beam chemistry options supports accelerated milling, selective milling, deposition and enhanced imaging with both ion and electron beams.

Integrated Preparation, Imaging and Analysis
The Helios NanoLab 400S is the ideal platform for S/TEM sample preparation and imaging. The in-situ STEM detector permits real time monitoring of the STEM image while thinning, for ultimate control of the preparation process and localization. The Sidewinder ion column's ability to maintain small beam diameter at less than 1 kV enables low-energy, grazing-incidence final clean-up to remove surface damage induced by higher-energy milling. The 400S provides STEM capability at accelerating voltages up to 30 kV, or the sample may be transferred to a high voltage S/TEM for ultra high resolution imaging and analysis.

Extensive automation permits unattended preparation of multiple site-specific S/TEM samples in a single session at a cost-per-sample competitive with conventional SEM bulk sample preparations. Optional X-ray (EDS or WDS) spectrometers offer compositional analysis in thin samples with resolution down to 30 nm. Automated slice and view capability can acquire a sequence of cross sectional images and reconstruct a three-dimensional model of the cross-sectioned volume that can be viewed and virtually re-sectioned in any direction.

All bleeding-edge IC manufacturers developing new processes and introducing new materials at 65nm and below need the ability to accurately inspect and measure their product. In order to do this, R&D labs require the ability to cut into and inspect cross-sections of the finished product. An Ultra High Resolution DualBeam system (combining SEM and FIB) is required to accurately find, cut, and image these parts.

In some cases, the development and process engineers can get the data they need by looking at the surface of the cross-section using very low energy electron beam imaging. The Helios NanoLab 400S offers the highest resolution SEM column in a DualBeam at very low beam energies (down to <1kV) to enable engineers to get the best cross-section image possible with minimal sample damage. For more advanced structures that require higher resolution TEM imaging, the Helios NanoLab 400S is also the most advanced DualBeam available for creating high quality TEM lamellae. A thin lamella (in some cases less than 30nm thick) with minimal sidewall damage from FIB milling is required by the TEM to enable accurate structural and analytical results. The exclusive Flipstage and in-situ STEM detector combined with very low kV Sidewinder FIB milling on the Helios NanoLab 400S allow leading IC manufactures to create the best possible TEM samples which in turn enable faster, higher-yield process node shrinks.

The Helios NanoLab 400S has been adopted by nearly all leading and bleeding edge IC manufactures since its release in mid-2007.

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Mfg Vision
Floorvision yield management software

The FloorVision software tool provides faster resolution of semiconductor yield issues through integrated Yield Management, SPC (Statistical Process Control)and rapid root cause analysis. In FloorVision, customers have fab, wafer sort and test data linked seamlessly using genealogy.

Customers can manage product performance during characterization, yield ramp and volume production. Supply chain visibility and traceability of parts are improved. All reporting is dynamic, interactive and shareable with teams across the world in a secure environment. User-defined exception reporting automatically communicates product performance variances, increasing productivity and satisfaction levels amongst product engineers.

With its highly scalable configuration, this web 2.0-based data-management system integrates Manufacturing Execution Systems (MES) based reporting, genealogy, semiconductor fabrication, wafer probe and test data in a seamless flow across multiple geographies.

This means that engineers, managers and executives can accurately capture critical data, speedily determine the root cause of product failures, efficiently correlate failures to process parameters, and quickly disseminate thorough yield reports to team members and other key decision makers.

The result: reduced downtime from process failures, improved productivity for product and test engineers, and lower IT costs. Among the key attributes of the FloorVision tool are: extremely fast data processing (results are available to the user in seconds), ease of use (with a little training any customer employee, not just yield management experts, can be up and running with the tool), and stability (Floorvision tool is server based).

Feedback from multiple clients is that this yield management tool is "technically the best on the market". It combines leading edge features with the ability to analyze results virtually in real time. This provides customers the ability to increase productivity, lower IT costs and ultimately improve margins on their products.

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Virage Logic Corporation
Self-Test and Repair (STAR) Yield Accelerator

Virage Logic's Self-Test and Repair (STAR) Yield Accelerator, announced on October 22, 2007, is a new option available for the STAR Memory System, Virage Logic’s industry-leading embedded test and repair solution. The STAR Yield Accelerator provides a complete solution for automated silicon verification, vector generation, silicon analysis, and yield ramping of embedded memories. Integrated with the industry leading STAR Memory System embedded test and repair solution, the STAR Yield Accelerator bridges the design and manufacturing disciplines to enable automated test vector generation, silicon analysis, fault isolation and classification to be used at the critical semiconductor tape-out, bring-up and volume manufacturing stages, dramatically reducing silicon time-to-test, time-to-product bring-up, and time-to-volume production.

The STAR Yield Accelerator family of products consists of the STAR Verifier, STAR Vector Generator, STAR Debugger, and STAR Yield Analyzer, which can be licensed separately or in a package. Leveraging the infrastructure of the STAR Memory System, the STAR Yield Accelerator automatically generates vectors for test equipment and provides fault analysis and root-cause failure guidance based on silicon test results.

Virage Logic’s STAR Yield Accelerator has capabilities and benefits that address the needs of test, product, and process engineers using the STAR Memory System. Automation support for verification and vector generation provides value to all design and test engineers implementing the STAR Memory System for memory test and repair. Automation to easily enable silicon debug through embedded memories is an essential capability for test and product engineers to quickly and easily identify and isolation silicon related issues. Automation to aid in failure trend analysis is a value added capability for any company that is shipping high volume products or any silicon manufacturer that is producing a high volume of wafers. The ability to even incrementally improve yield can dramatically impact profitability.

The STAR Yield Accelerator is proven to dramatically reduce silicon time-to-test, time-to-product bring-up, and time-to-volume production. Through preliminary engagements with several key semiconductor customers at 90nm, 65nm, and 55nm process nodes, the STAR Yield Accelerator has demonstrated its ability to meet design requirements of integrated device manufacturers (IDM), fabless and foundry customers. The STAR Yield Accelerator rapidly, cost-effectively and accurately identifies, analyzes, isolates, and classifies memory faults as designs are readied for transition from first silicon to volume manufacturing. By automating this process within the existing development workflow, STAR Yield Accelerator works with the STAR Memory System to speed system-on-chip (SoC) time-to-volume and dramatically boost yield percentages. The STAR Yield Accelerator can reduce silicon bring-up by months, reducing overall time-to-volume production.

STAR Yield Accelerator’s verifier, vector generator, and debugger components automatically generate vectors for test equipment and provide fault analysis and root-cause failure guidance based on silicon test results. Using STAR Yield Accelerator, manufacturers can rapidly and directly analyze failures manifested in embedded memories and inspect the physical location and class of each fault to determine the root cause without involving the intellectual property (IP) vendor or SoC designers.

Offering capabilities far beyond conventional physical de-processing and manual analysis, the STAR Yield Accelerator can pinpoint the exact physical location of memory faults and provide guidance of the root cause. By enabling engineers to troubleshoot yield issues in a secure and efficient manner, the STAR Yield Accelerator protects both manufacturers’ sensitive process data and the designers’ closely guarded design data.

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Vistec Semiconductor Systems GmbH
LMS IPRO4

Vistec's LMS IPRO4 is a fully automated mask metrology system. It is capable to measure registration (overlay on reticles) as well as critical dimensions (CD) in transmitted light or in reflected light at i-line (365nm).

The LMS IPRO4 is designed to support mask metrology requirements of the 45nm node. The system is famous for its measurement performance and reliability, for its straight forward user interface and its comprehensive data evaluation software.

The LMS IPRO4 can be equipped with an optional 300mm wafer chuck in order to qualify thoroughly pattern placement of any wafer lithography tool, either scanners or direct write e-beam systems.

The system is equipped with a 904 nm infrared laser auto focus (LAF) diode. It is used in conjunction with a TV autofocus system for obtaining edge intensity profiles and ultimately edge locations in a quality that has not been possible ever before: Experimentally measured positions of structures as small as 0.13 micron showed excellent results.

Superb Mechanics:
One of the main assets of the LMS IPRO4 is the stage. The LMS IPRO4 measures up to a maximum of 300 mm in both the X and Y directions. The plate holders are constructed of a low expansion ceramic substance, and the optical head and other mechanical components are made from "Invar" - a low expansion metal.

Safe Substrate Handling:
The automatic substrate handling system with an eight position magazine allows you to temperature acclimate substrates in the environmental chamber prior to measurement. An optional SMIF package is available for particulate control. The SMIF system can handle 6025 reticles and is capable to rotate substrates in 4 different orientations. The integrated reticle flipping unit enables most convenient substrate handling. Manual SMIF pod opening even in case of measuring pelliclized reticles is redundantized.

Wafer substrates are loaded manually onto a loading station equipped with a wafer vacuum chuck. This chuck can then be placed automatically onto the measurement stage or into the eight position magazine for temperature acclimation or batch processing.

Automatic Operation:
You can program the batching of multiple measurement jobs on multiple substrates for automatic operation. The batch processing programming runs either on-line or off-line. The system can also be programmed in batch mode to automatically process measurement output results for input into Deva or LMSASCII according to pre-determined templates. With the LMSASCII software program you can output measurement results data in fully customizable formats and export them into other programs such as Microsoft Excel. Utilizing third party software users can remotely operate and/or monitor the LMS IPRO4 via network.

• Unique and highly innovative product
• Continuous adaptation to customer needs over many tool generations
• Measurement performance significantly better than specifications
• Reliability
• Smooth installation of beta-site system

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VLSI Standards, Inc.
NanoCD Standard

NanoCD Standard - The NanoCD (NCD) is the first commercially available standard to provide line width accuracy calibration at the 45 nm, 65 nm, 90 nm and 130 nm nodes (and 32 nm coming!). Use these standards for tool matching, calibrating the width of a CD-AFM tip, or CD-SEM diagnostics. The NanoCD consists of a small chip containing a single isolated line 4 mm long (3 mm certified), offering thousands of distinct measurement sites. Chips are fabricated at VLSI Standards using a patented technique that results in lines with high uniformity and low associated uncertainty, unachievable through conventional lithography methods. For compatibility with wafer handlers, the chip is mounted to an etched pocket of a silicon wafer carrier. Global alignment marks, rulers and pattern recognition features extending from the chip to the wafer ensure that the target is always located, and measurements can be repeated.

The width of the line, or the Critical Dimension (CD), is certified with TEM and is traceable to NIST and to the international system of units (SI) through the atomic lattice spacing of single crystal silicon.

Product Specifications
Nominal CD Values - 25 nm, 45 nm, 70 nm, or 110 nm.

Accuracy - 25 nm ± 0.5 nm, 45 nm ± 0.7 nm, 70 nm ± 0.7 nm, 110 ± 0.8 nm

Material of CD line

Amorphous Silicon

Length of Line - 3 mm certified

Defectivity of Line - 5% Max. (150 µm of total 3,000 µm)

Traceability - Traceable to the SI units through the atomic lattice spacing in the silicon crystal by TEM

SEMI Specification Silicon Wafers - 200 and 300 mm diameter wafers available in X or X,Y configuration.

This product has allowed for a vast improvement in the precision and matching of production CD-SEMs and has enabled the use of the CD-AFM for accurate linewidth measurement during process development and line monitoring, both in the wafer fab and in the mask shop. Prior to the release of NanoCD, the absolute accuracy of the CD-AFM linewidth metrology was limited to about 5 nm, which does not meet the ITRS roadmap requirement. The only available solution to accurate linewidth metrology was cross-section TEM, which is destructive, time-consuming, and expensive. With the use of the NanoCD, Critical Dimension metrology tools can exceed the ITRS requirements for linewidth metrology, in a fast, non-destructive, and inexpensive way. CD-SEMs have many critical system parameters that may unexpectedly change over time. These include beam size adjustment, auto focus precision adjustment, depth of field adjustment, astigmatism, electronic filtering algorithms, and tilt and columns tage alignment to name a few. The NanoCD Standard can be used on a daily basis to discover and diagnose these potential variables. With CD-AFMs, it is paramount that the user know the size and working condition of the probe tip being used on the instrument. With the NanoCD, the user can now measure the certified linewidth, and thereby calibrate the tip width. This ensures that the CD-AFM provides accurate measurements. The same calibration procedure is to be followed periodically, because the tip width changes over time due to wear. There are no commercially available competing products. The only alternative for accurate linewidth metrology is cross-section TEM. The NanoCD is also NIST-traceable, allowing users to meet quality system requirements. The certified lines have a high accuracy (<1 nm uncertainty), low line edge roughness, high contrast, and a large measurement area (4 mm in line length). The standard is available in various configurations such as wafer form for semiconductor & MEMS manufacturers, Mask form for photomask manufacturers and lithography concerns, and sample mounted for users of analytical instruments.

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ASM America, Inc.
Pulsar 3000 ALD Module

The Pulsar 3000 ALD module is a single wafer reactor that enables deposition of high-k materials for transistor and capacitor products. Atomic Layer Deposition (ALD) is a surface controlled layer by layer process for the deposition of thin films with atomic layer accuracy. The ALD process can be used to produce single or multiple layers of oxides, nitrides, or metals. The surface controlled growth mechanism provides excellent step coverage on aspect ratios as large as 100:1 with no pinholes. The Pulsar 3000 module is being used to deposit dielectric and metal films for DRAM trench and stacked capacitors, diffusion barrier layers for FeRAM, dielectric layers for magnetic head applications, and most recently, for dielectric and metal deposition in CMOS high-k/metal gate technology.

The Pulsar 3000 is a bridge tool capable of processing substrates from 150 mm to 300 mm in diameter. Multiple Pulsar 3000 modules can be integrated on a cluster platform and the modules can run either serially for extreme flexibility and complex stacked films, or in parallel for a high productivity solution for ALD deposition of a single film. Although ALD has been historically viewed as being a slow process, the Pulsar(r) 3000's unique delivery system and cross-flow reactor design has enabled development of high speed ALD processes with single reactor throughputs as high as 60 WPH for 100 A films. Futher more, the module is equipped with 6 sources capable of running solid, liquid and gaseous precursors. At a module footprint of less than 10 ft², the Pulsar 3000 is highly compact and flexible ALD system for research, development and high volume manufacturing. The Pulsar 3000 module is the first product to be used for high volume manufacturing of hafnium based high-k dielectrics for CMOS gate applications - enabling the first fundamental shift in material choice for the CMOS gate dielectric since the invention of the modern transistor.

The module has demonstrated long term manufacturability for the deposition of these new gate dielectrics. Defect performance is typically less than 10 adders @ 0.10 um and film thickness is controlled to less than 1 Angstrom range across a 300 mm wafer. The reactor is unaffected by invasive maintenance and does not require lengthy tuning runs or dummy wafers when processes are restarted after idle or maintenance. The Pulsar 3000 enables high-k gate dielectric deposition for replacement gate technologies and also enables uniform deposition of extremely thin capping layers (< 5 A) that allow use of high-k/metal gate technology in conventional gate first CMOS process flows. The capping layers can be deposited in-situ to eliminate any issues related to degradation of the high-k interface due to air breaks.

The Pulsar 3000 enables high-k dielectric deposition at low thermal budgets (< 400 C). This is particularly important for sensitive applications such as the CMOS gate dielectric, where PVD and other plasma based processes can result in film damage, and high temperature processes such as MOCVD can lead to interfacial layer thickening. The ALD process also provides the best film uniformity, purity and composition control for extremely thin film layers (<20 A). The Pulsar 3000 is the only high-k tool in production with HfCl4, a solid source. Use of halide based precursors eliminates the risk of carbon contamination in the dielectric, which has been proven to reduce the performance of these films. The reactor is a cross flow design, which is the best configuration for efficient purging of the reactor. The reactor design has been optimized to deliver laminar flow with minimal eddy currents and recirculation cells. This has resulted in a module with unrivalled defect performance and film uniformity, making the module a technology enabler for critical, yield sensitive applications such as the CMOS gate dielectric.

The module has the capability to run up to 6 sources (2 gases, 2 liquids, 2 solids) - resulting in a very flexible toolset for complex film stacks.

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Aviza Technology, Inc.
Versalis fxP-Integrated Process Solution for 3D-ICs

Aviza’s Versalis fxP system is a single wafer 200/300 mm cluster tool that integrates multiple processes (including etch, PVD and CVD) all on one platform. Targeted for advanced research and development (R&D) activities for 3D-IC devices, Versalis fxP offers a route for customers to develop their Through Silicon Via (TSV) technology and easily migrate their processes for high-volume production. This “one-stop shop” solution enables customers to save money by investing in less CapEx for R&D, minimize installation costs and make efficient use of fab area.

The Versalis fxP is based on Aviza’s production-proven single wafer platform. Its individual modules such as deep silicon etch, PVD and CVD have all been proven in high-volume manufacturing for various applications including wafer level packaging, MEMS and power semiconductors. Customers can benefit from Aviza’s process expertise in these areas in order to meet their stringent process specifications. For example, Aviza’s deep silicon etch is high rate, while Aviza’s PVD re-sputtering process has been developed to give the continuous via sidewall coverage needed for the plating step.

The Versalis fxP system allows R&D users to link processes in a way that would not be possible on traditionally configured single-process systems. On the Versalis fxP, users can link separate processes without breaking vacuum to discover potential performance benefits, and then apply those findings to optimally configure production tools.

Aviza sees 3D-ICs as a growth market to enable smaller factor devices (such as PCs, PDAs, mobile phones and other consumer products) with increased functionality and improved electrical performance. By leveraging the company’s process expertise in the areas of etch, PVD and CVD, we believe that Versalis fxP offers a unique solution to the R&D community focusing on 3D-ICs and TSV technology. On one platform, customers can develop their TSV processes in a cost-effective and efficient manner with the ability to seamlessly migrate these processes to the production environment. Packaging is a cost-driven activity and Versalis fxP significantly cuts R&D CapEx over traditionally configured single-use equipment. Aviza has already shipped a Versalis fxP tool carrying etch & CVD modules and is seeing significant interest for Versalis fxPs from Advanced Packaging houses, foundries and IDMs for the integration of etch, CVD & PVD technologies.

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EV Group (EVG)
EVG®150 NanoSpray Coating System

• Designed for fully-automated high topography spray coating.
• Patent pending spray coating technique for coating very small and deep patterns
• Unique spray process that is based on a spray mist created by ultrasonic nozzles
• Significant improvement in refined dispense and targeted positioning of the spray stream
• Supports wafers up to 300 mm diameter
• Homogenous coatings of features 300µm deep and 100µm diameter

The development of this novel system was driven by the emerging 3D Interconnect (3D IC) applications based on Silicon TSV (Through Silicon Via) technologies. This new milestone in photoresist application will enable users to carry out further lithography steps at the bottom of vias to create through wafer interconnects and allow a new bandwidth of applications throughout many technologies in Semiconductor processing markets. While the coating of vertical features is common practice in MEMS technology, it has also recently been adopted in emerging packaging applications based on TSV technology, used in the advanced packaging and interconnect arenas. Vias are used to interconnect the active front side of the wafer to the backside and further on to the pins of the specific wafer level package. This coating technology was first realized by EVG on their EVG100 series coating equipment by development and integration of new spray technology and techniques.

First systems have been installed at major customers and are being used to manufacture CMOS Imaging Sensor (CIS) packages based on TSV technology.

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MATECH
WaveEtch Advanced Wet Processing Tools

MATECH’s WaveEtch systems is unique because of the new capabilities they bring to the wet processing toolset of the semiconductor and photovoltaic industry.

These new capabilities include the ability to texture surfaces using wet processes, the ability to clean, thin, etch, and stress relief conventional as well as ultra-thin wafers (50 um and below), inherent single-sidedness, reduced chemical usage and reduced environmental impact. The WaveEtch systems can also wet process very thin wafers that are distorted or warped. All this wet processing power is embodied in a flexible, single tool capable of multiple processes and high throughput-up 1200 to 2400 substrates per hour. Substrates of virtually any size and shape can be easily processed by the WaveEtch systems.

The system’s LinearScan technology effectively eliminates virtually all transport-related and centrosymmetrical non-uniformities, which plague spin/spray or immersion processes.

At present, no commercial system provides these advanced capabilities in a single, cost efficient platform.

The WaveEtch LinearScan technology has also important applications in photovoltaic or solar cell manufacturing; from saw damage removal, to surface texturing for efficiency increase, to thinning the solar cell substrate.

The WaveEtch systems simplify the manufacturer’s toolset, lower chemical usage and its associated purchase and disposal costs, as well as often easing environmental regulatory compliance, resulting in overall production and costs of ownership (COO) reduction.

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Microcontrol Electronic srl
Photopolymer film lamination system

Leonardo 300 series, fully automatic bridge tool 200 – 300 mm system. Used to laminate permanent and not permanent photopolymer films in wafer level packaging and TSV processes. Used in MEMS application to create multilevel structures on silicon or any other substrates including glass and containing heavy topography or pre-etched features. All process parameters are fully controlled and loadable in recipes.

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Rudolph Technology
The NSX Series

The NSX Series is a high-throughput and repeatable macro defect inspection solution used throughout the device manufacturing process. Macro defects (defects 0.5 micron and larger) can be created during wafer manufacturing, probing, bumping, dicing, or by general handling, and can have a major impact on the quality of a microelectronic device. The NSX quickly and accurately detects yield-inhibiting defects, providing quality assurance and valuable process information. This information may be transferred to yield management programs, including Rudolph's DMS Decision software and fabwide DMSVision software for further analysis and review, reducing manufacturing costs and time to market.

Overview

• New NSX 100: High throughput inspection for 200 mm applications
• Automated, 100% advanced macro defect inspection
• Fast and consistent 2D bump inspection
• Provides process and defect information for enhanced process control and product consistency
• Features an easy-to-use Windows-based user interface
• Time-tested applications in semiconductor, optoelectronics, wafer bumping, data storage, micro electromechanical systems (MEMS) and micro display markets

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Alchimer
Electrografting process for TSV metallisation

Electrografting is Alchimer’s breakthrough proprietary process for the initiation and growth of thin films on conducting and semiconducting surfaces. It works by ‘grafting’ molecular precursors to a variety of materials, through creating covalent bonds between the materials.

Electrografting technology can be used to deposit copper seed layers in through silicon vias (TSVs), using a material called eG ViaCoat. Electrografting can produce conformal, ultra-thin, uniform and adherent copper seed layers in the 50 to 500nm range, even on resistive barriers. The production of such copper seed layers for high aspect ratio TSV metallization has been a major roadblock to 3D packaging adoption – PVD (physical vapor deposition) processes have already reached their limitations in terms of producing continuous layers for TSVs with aspect ratios of 3:1 and above.

Electrografting technology demonstrates continuous sidewall and bottom coverage even on highly scalloped TSV etch profiles, and at aggressive TSV aspect ratios. Reliable metallization of TSVs with aspect ratios of 13:1 is now possible.

Electrografting is a wet electrochemical process based on specific organic precursors. Because the size of the precursors being introduced is in the order of 0.5nm, it provides a method of depositing material at the scale required for leading edge process nodes, both today and in the future. The substrate is placed in contact with a wet solution and the process operates by applying a small electric current: due to the very nature of the molecular precursors and of the reaction mechanisms they can undergo, unusually small amounts of current - of the order of 1 to 10;A/cm2 - are enough to trigger the process uniformly at any point of the surface of the substrate. This is called the electro-initiation step, which involves electronic transfer from the surface to the adsorbed precursors at chemical bond distance.

Once the surface is “seeded” with adsorbed activated moieties, the same precursors can undergo alternative chemical reaction paths which lead to the formation of the desired layers: while the process is controlled by the electro-initiation step, subsequent steps immediately following the electro-initiation may involve purely chemical reactions depending on the nature of the molecular precursor. In any case, the electro-initiated nucleation secures the growth of the film in a conformal and uniform manner. Through controlling just the current, Alchimer is able to demonstrate the deposition of ultra thin films of less than 10nm, with high uniformity across surfaces over a broad range of substrate resistivities.

This process can easily be implemented using industry-standard copper electroplating equipment, removing any requirement for additional capital expenditure; the process has been demonstrated on existing high-end 12-inch tools all the way down to legacy 6- or 8-inch equipment. The process is also compatible with CMP and other post-processing steps required for chip packaging.

Electrografting is compatible with standard barrier materi