Advanced Diamond Technologies, Inc.
Ultrananocrystalline Diamond Wafers

For decades designers and engineers have sought to harness the unsurpassed properties of diamond for MEMS and electronic devices. Despite the keen interest, diamond has been notoriously difficult to work with, is prohibitively expensive for mainstream applications and there hasn’t been a reliable supply. Enter UNCD Wafers.

UNCD Wafers from Advanced Diamond Technologies, Inc. suddenly make diamond affordable and accessible for MEMS and IC applications. UNCD (for ultrananocrystalline diamond) is the only phase-pure nanocrystalline diamond film in the world and is comprised of diamond grains that are as small as 5 nm in diameter - a billion-fold smaller in volume than in traditional diamond films. UNCD differs from other nanocrystalline diamond films in that other films are comprised of graphitically-bonded material intermixed with crystalline diamond grains. UNCD, in contrast, has no amorphous or graphitic phases. UNCD Wafers capture the hardness, modulus and other extreme properties of natural diamond but are also smooth and have very low internal stresses making them suitable for a variety of applications. UNCD Wafers meet basic foundry level standards including wafer bow, particle count and thickness uniformity.

Most MEMS devices are based on silicon due to the availability of microfabrication techniques developed for the integrated circuits industry. Diamond has unsurpassed bulk and surface properties that exceed those of any other material, and UNCD Wafers are the base material for MEMS device fabrication. The availability of 200 mm UNCD Wafers and standard microfabrication techniques for processing (reactive ion etching) provide for the ability to manufacture diamond devices in a standard foundry environment.

UNCD Wafers are a critical enabling technology because they provide the mechanism for designers to begin building diamond devices today.

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Alchimer
eG ViaCoat material for TSV metallisation

eG ViaCoat is the enabling material for Alchimer's breakthrough proprietary electrografting process. eG ViaCoat has been developed specifically for the metallisation of high aspect ratio through-silicon vias (TSVs) used in advanced 3D packaging applications.

eG ViaCoat is a mild acidic aqueous copper electrolyte solution that enables the deposition of ultra thin, homogeneous, uniform, adherent and conformal layers. The material is specifically formulated for creation of copper seed layers on widely adopted barrier layers (including, but not limited to, PVD, CVD and ALD deposited Ta, TaN, Ti, TiN, WN, Ru and bi-layers). Electrografting is a wet electrochemical process based on specific organic precursors enabling the initiation and growth of thin films on conducting and semiconducting surfaces. The process can produce conformal, thin, uniform and adherent copper seed layers, even on resistive barriers. It works by 'grafting' molecular precursors to a variety of conductive materials, through creating covalent bonds between the materials.

Because the size of the precursors being introduced is in the order of 0.5nm, it provides a method of depositing material at the scale required for leading edge process nodes, both today and in the future. The substrate is placed in contact with a wet solution and the process operates by applying a small electric current: due to the very nature of the molecular precursors and of the reaction mechanisms they can undergo, unusually small amounts of current - of the order of 1 to 10 µA/cm² - are enough to trigger the process uniformly at any point of the surface of the substrate. This is called the electro-initiation step, which involves electronic transfer from the surface to the adsorbed precursors at chemical bond distance.

Once the surface is "seeded" with adsorbed activated moieties, the same precursors can undergo alternative chemical reaction paths which lead to the formation of the desired layers: while the process is controlled by the electro-initiation step, subsequent steps immediately following the electro-initiation may involve purely chemical reactions depending on the nature of the molecular precursor. In any case, the electro-initiated nucleation secures the growth of the film in a conformal and uniform manner. Through controlling just the current, Alchimer is able to demonstrate the deposition of ultra thin films of less than 10nm, with high uniformity across surfaces over a broad range of substrate resistivities.

One of the first applications of electrografting technology is copper seed layers in TSV metallisation. eG ViaCoat has the unique ability to enable ultra-thin and conformal copper seed layer deposition in the 50 to 500nm range, a major roadblock to 3D packaging adoption due to the dry vacuum processes in use for the past 40 years. This process can easily be implemented using industry-standard copper electroplating equipment, removing any requirement for additional capital expenditure.

PVD (physical vapor deposition) processes have already reached their limitations in terms of producing continuous layers for through silicon vias with aspect ratios of 3:1 and above. In practice, this is a major roadblock to the adoption of advanced 3D packaging. Alchimer's electrografting process using eG ViaCoat demonstrates conformal sidewall and bottom coverage even on highly scalloped TSV etch profiles, and at aggressive TSV aspect ratios. Reliable metallisation of TSVs with aspect ratios of 13:1 is now possible.

eG ViaCoat enables significant reductions in cost of ownership (CoO) compared to dry vacuum processes. For example, for 10:1 aspect ratio TSVs, the CoO of Alchimer's electrografting process is 85% less than that of a traditional PVD process. The cost advantage increases further at higher aspect ratios and electrografting can be applied using industry-standard copper electroplating equipment, eliminating new capital expenditure.

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Honeywell Electronic Materials
Reusable Thermal Interface Materials

This material provides outstanding, repeatable thermal performance over many thousands of test cycles. The material is used during the semiconductor burn-in testing process, which is a critical step in verifying that newly created microchips meet lifetime and performance requirements.

During the burn-in process, sample chips are subjected to extreme heat. Burn-in materials are used to transfer that heat to the chip for the test. Traditional materials that have been used for this application provide good thermal performance, but their use is limited to a single cycle and a residue is typically left behind that must be cleaned before the next test.

Honeywell's material eliminates the cleaning step and, since it can be used repeatedly, reduces material usage. The new material also has superior performance to alternative multi-use thermal interface materials used for burn-in. Besides the described application as a burn-in material, Honeywell's material can also be used in a broad spectrum of processes as a thermal interface material (TIM) for thermal modules or assembled packages.

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SILECS, INC.
New use of spin-on dielectric materials to enable new generation of CMOS sensors

Increasing the performance requirements in CMOS image sensors (CIS) for digital cameras is driving a need for improvements in both the optical portion of CIS devices and the durability of the camera module assembly.

Enabling materials innovator, Silecs, has developed two novel uses of Spin-on Dielectric (SOD) materials to accomplish both of these objectives. Each of the new approaches uses SOD in the construction of the optical stack, in contrast to the organic photo resist-like materials conventionally employed. In the first method, a vertical light guide (VLG) structure is formed in the device backend and filled with high refractive index SOD (RI=1.65 @ 633nm) to improve optical performance. The second method employs a low refractive index SOD (RI~1.28 @633nm) topcoat, which enables easier micro lens engineering and optimization, and also offers the advantage of protecting the organic micro lens with a glass-like layer.

Silecs has applied the VLG technique to successfully integrate a VLG structure in a 0.18um and below image sensor structure and compatible with both Al and Cu backend. Unlike conventional approaches, the resulting optical stack is not diffraction-limited. Excellent planarity above the optical elements was achieved, eliminating the potential need for CMP, and dark current performance was not compromised.

Silecs has likewise demonstrated the effectiveness of the second technique, using low RI SC500 as a topcoat. The glass-like behaviour of this SOD material offers the advantage of micro lens protection during sawing and improves epoxy base-like packaging compatibility. The SOD was engineered to enable excellent planarity or conformality above micro lens array with superior film quality. The use of a low refractive index topcoat enables focal lengths in the intermediate range (between backend without topcoat and backend with a common organic topcoat).

Further, the technique introduces an extra degree of freedom in the design of optical system focal length through control of the SOD bake conditions. When the focal length is kept the same for an existing integration scheme with or without topcoat, the same optical performance is obtained. This is achieved by adjustment of micro lens height for each case. Again, there is no degradation in dark current performance.

The two integration schemes (VLG and lens topcoat) are complementary, and when used in combination, will help enable a new generation of more efficient, sensitive and reliable CMOS sensors that have a smaller footprint. The work was conducted at Silecs' state-of-the-art production facility in Espoo, Finland. Here, Silecs' advanced enabling materials are developed and manufactured in semiconductor-like clean-room conditions, mirroring the production environments of the company's microelectronics manufacturing customers.

Process represents a unique new way to use spin-on dielectric materials; process resulted in significant performance improvements; process enables a new generation of more efficient, sensitive and reliable CMOS sensors with a smaller footprint. Work was conducted with leading customer in Silecs' state-of-the-art mfg facility in Espoo, Finland with production conditions that mirror microelectronics\' clean-room environments. Silecs is a thriving emerging player in the highly competitive electronic materials industry.

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DuPont/EKC Technology
Copper/low-k post-etch residue remover

The 21st century has ushered in a move to more sustainable technologies and processes. But the semiconductor industry still demands uncompromising performance throughout the manufacture process. DuPontT CuSolveT EKC520T copper post-etch residue remover offers a safer and more sustainable alternative for customers that does not compromise on cleaning and gives repeatable high up time, high yielding, high throughput and manufacturable results.

CuSolveT EKC520T copper post-etch residue remover was introduced by DuPont EKC Technology, part of DuPont Electronic Technologies, to address the key challenges facing its customers as they continue to push the boundaries of IC fabrication. Working in close collaboration with customers EKC identified novel solutions to these challenges offering a step change improvement over previous generations of cleaning solutions.

EKC520T copper post-etch residue remover does not rely on "under etch and release" mechanisms to remove post-etch residues. Instead, the optimised active components of the chemistry selectively convert and remove these residues. This selectivity is key to the success of EKC520T as it minimises CD loss without having to trade off cleaning efficiency.

EKC520T delivers unparalleled performance and can do so with significant increases in throughput by eliminating "spin off" steps and reducing rinse times with a corresponding beneficial impact on overall cost of ownership. Such improvements are possible because of the aqueous, low viscosity nature of the clean. Furthermore, because of this and the broad process window offered by EKC520T it can readily be integrated into production without costly tool retro fitting.

EKC520T is safer and more sustainable in customer processes, as it can be disposed to drain after neutralization under the applicable laws of most jurisdictions, unlike many solvent fluoride cleaners.

CuSolveT EKC520T is one component of DuPont EKC Technology's offerings for Cu integration cleaning solutions including post etch residue and post CMP cleaning. The CuSolveT product line builds on DuPont's core competence in developing novel yet practical solutions for today and tomorrows challenges.

EKC Technology is part of DuPont Electronic Technologies, a leading supplier of electronic materials, including materials for the fabrication and packaging of semiconductors, materials for hybrid, rigid and flexible circuits, and materials for advanced displays. For more information, please visit electronics.dupont.com.

DuPont is a science company. Founded in 1802, DuPont puts science to work by creating sustainable solutions essential to a better, safer, healthier life for people everywhere. Operating in more than 70 countries, DuPont offers a wide range of innovative products and services for markets including agriculture, nutrition, electronics, communications, safety and protection, home and construction, transportation and apparel.

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Entegris
Ultrapak Edge Guard wafer shipping box

The Ultrapak Edge Guard 200mm wafer shipping box is said to reduce edge contamination, with 50% or more reduction in particle contamination from edge contact. This is expected to prevent particle-induced device defects during circuit fabrication. Designed for re-use, the shippers have horizontal and vertical robotic pick-up flanges on the cassette, while centre notch track alignment and H-bar features ensure accurate equipment interoperability.

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Ferro Electronic Material Systems
Self-stopping CMP slurry

The SureStop 8500 self-stopping chemical mechanical planarization slurry for inner layer dielectric materials provides a reported planarization efficiency of >95% with an increased over-polish window and eliminates the need for endpoint detection. The 8500 can be used to simplify planarization processes that employ reverse-mask etchback steps. This slurry contains chemistries that exhibit topography-dependent polishing behaviour that coat the wafer surface to automatically stop polishing when the topography has been removed. The slurry removes oxide topography (“Up” oxide) of up to 20,000A in step height with very little removal of the oxide at the bottom of trenches (“Down” oxide) for high planarization efficiencies throughout the polish. SureStop 8500 provides step height removal of >5000A/min and blanket removal rates of <300A/min.

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Okmetic Oyj
G-SOI - gettered SOI substrates for integrated MEMS and CMOS processes

Okmetic has developed a new thick BSOI product with built-in gettering properties (G-SOI). The wafer is designed for integrated MEMS and CMOS processes. The gettering effect is achieved by a buried polysilicon layer between the active layer and the buried oxide of a BSOI structure.

The push towards G-SOI product development came from a gate oxide integrity problem that was encountered when CMOS processes were implemented on standard thick BSOI wafers. It took the form of midfield breakdown sites while testing the gate oxide breakdown voltage, for example. The occurrence of gate oxide failure was traced back to the starting material, and in particular to the metal impurities in the active layer. The active layer has no gettering sites, and the buried oxide in a BSOI structure prevents diffusion of most transition metal impurities out of the active region into the bulk or the back surface of the wafer where the gettering sites are normally formed. To find a solution that is layout-independent, a thin polysilicon layer was added between the active silicon layer and the buried oxide layer.

Gettering efficiency was estimated based on DLTS measurement of iron (Fe) concentration in the active region after intentional contamination of BSOI wafers. A thin polysilicon layer in a BSOI wafer reduces the Fe concentration below the detection limit 1E+11 at/cm3, compared to 1.9E+13 at/cm3 in a standard BSOI wafer, implying gettering efficiency > 99%. The result is independent of the polysilicon film thickness from 0.2 m to 1.0 m. A high temperature process simulation was carried out based on a process cycle with 24 h at 1000°C, and a maximum temperature 1150°C for 4 h. The gettering efficiency analyzed after the high temperature processing of wafers was > 97%.

The buried polysilicon layer solves the gettering problem for metal impurities in bonded SOI wafers for integrated MEMS and CMOS processes where SOI is required for the realisation of the sensor element. Testing of wafers in CMOS processes show clearly better gate oxide integrity than in standard BSOI wafers, and in fact it is as good as in conventional bulk silicon wafers.

The wafer is designed for integrated MEMS and CMOS processes where the SOI is required for realisation of the sensor element. It can also be used in bipolar/BiCMOS applications.

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Camtek Intelligent Imaging Ltd.
Falcon line of automated wafer inspection & metrology systems

Camtek designs, develops, manufactures and markets technologically advanced, cost-effective systems and related software products that are used to enhance processes and yields. Camtek provides intelligent, automated optical inspection systems (AOI) to the Semiconductor Manufacturing and Packaging, IC Substrates, and Printed Circuit Board (PCB) industries. The company addresses the specific needs of each industry with dedicated solutions, based on a common core of intelligent imaging technologies.

The Falcon Family Advanced packaging of semiconductor devices depends on known-good-die to ensure high production yields and reliable device performance. Defects in the active die area or on interconnect pads, as well as deviations inbump dimensions and placement, may lead to device failure. Built upon over 20 years of experience in developing automated optical inspection (AOI) systems, the Falcon family addresses wafer-level inspection needs at production rates . The systems help semiconductor and MEMS manufacturers, bumping service providers, packaging foundries and test houses monitor their production processes and enhance yield. The Falcon systems measure and detect surface defects, as well as probe mark damage to bond pads. They measure deviations in solder and gold bump height, shape, size and placement. The systems inspect at pre-test, post-test, and post-dicing stages to check that dice are free of mechanical damage or contamination and that bond pads and flip-chip bumps can support a reliable interconnect. Camtek's modular, software-based architecture ensures flexible adaptation to each of our customer's individual needs.

Integrating 2D and 3D metrology and inspection systems on the same platform enables the Falcon to analyze bump co planarity or report statistical data for process monitoring.

An on-line statistical process control (SPC) package outputs relevant charts to assist quality assurance engineers identify root causes of defects, thus reducing process variations and enhancing production yields.

Falcon's high productivity results from its advanced electro-optics and massive computing power while its superb detection ability comes from its expansive set of sophisticated detection engines.

Performance, Responsiveness and Support: Performance:
- the Falcon family offers modular and software-intensive architecture, which enables flexible adaptation to customer-specific road maps and high versatility for standard and non-standard applications. This combination of performance and flexibility with ease of operation and reliability delivers to customers the optimal capital investment in inspection equipment.

Responsiveness:
The software-based, modular architecture of Falcon's systems enables addressing unique customer requirements with a high degree of customization, as well as providing an easy and cost-effective field upgrade package for existing equipment.

Support:
Camtek appreciates the value of strong field support at close proximity to the customer manufacturing plant. Therefore Camtek has established a world-class, customer support infrastructure. Organized in eight subsidiaries in the US, Europe, Japan, China, Hong Kong, Taiwan, Korea and Singapore, Camtek provides local service, spare parts, training, demo and sales services to its customers wherever they are located.

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Carl Zeiss SMT - SMS Division
E-beam Mask Repair System MeRiT MG 45

Carl Zeiss has developed a unique mask repair system based on electron-beam technology called MeRiT MG 45. This system overcomes the physical limits of almost all currently existing mask repair technologies e.g. focus ion beam, nanomachining or laser repair. With the continuing decrease of feature sizes on photomasks, the rising costs and the necessity to manufacture 100% error free reticle it is essential to have one industrial solution to perform reliable repairs on photomasks.

MeRiT MG 45 is the only viable solution meeting the challenging requirements for mask repair at the 45 nm node. The system allows opaque and clear defect repair in one platform. Thereby electron beam induced chemical gas phase reaction in ultra high vacuum for either selective etching or deposition of the respective mask materials.

Compared with previous technologies the MeRiT MG 45 uses a high resolution low energetic electron beam instead of ions or tips. This principle outperforms all other concepts. The process is only limited by the diameter of the electronic beam, which can in principle be downsized to sub nm range. Furthermore, the use of electron beams prevents radiation damage on the photomask.

The MeRiT MG 45 has an automated die to reference and die to database defect recognition. This allows a high level of automation to ensure reproducibility and efficiency. The repair process itself is partially automated as well. Depending on the material automated recipes chooses the appropriate precursor gases, either a local etch or a local deposition. Even defects which require complex combination of different etch or deposition steps can be repaired.

Photomasks typically have a surface which charges up when using electron or ion beams. The MeRiT MG 45 has a proprietary charge compensation technique to mitigate electron beam interaction with surface charging. A combination of annular secondary electron detector and annular energy selective backscattered electron detector, is mounted in the column. These detectors are specifically optimised for the purpose of high definition imaging. Furthermore they are used for ultimate precision and automated end-pointing of repair processes. As a result the MeRiT MG 45 system delivers the highest first pass yield of any repair tool known to the industry.

Employing electron-beam technology overcomes the physical limits of existing mask repair technologies and has the following strong advantages:

• Superior resolution and accuracy for all known kinds of repair
• Repair process causes no transmission loss and no contamination
• No mask structure modification during imaging allowing degradation-free review cycles
• E-beam induced chemical reactions without any sputter contribution
• Automated repair identification
• Automated repair endpointing
• High imaging signal-to-noise ratio allows excellent defect review
• Multi-node capability down to 45nm node and in some respects even below
• All-in-one-tool minimising processing overhead

MeRiT MG 45 enables the repair of all kinds of photomasks including phase shifting masks with tuneable phase and transmission matching. It is also suitable for next generation lithography such as NIL or EUV.

MeRiT MG 45 is the only photomask repair technology for 45nm node Enables manufacturing of advanced photomasks ZEISS photomask repair system led to paradigm shift in mask repair technology Optimizes yield of high-end photomask manufacturers Only concept which is applicable for the 45 nm node and down scalable to the 22 nm node (and maybe below).

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Metryx Ltd
The Metryx Mentor

The Metryx Mentor provides a new generation of metrology tool based on innovative mass metrology for materials development and SPC / APC. The Mentor is designed to monitor changes in process performance, and quickly determine whether device manufacturers’ process steps are operating correctly by measuring the mass change of any product wafer through a process step. Simple statistical analysis of the measurement data enables the tool to reliably and accurately identify process changes after deposition, wet or dry etch, or CMP Processing. The tool achieves measurements down to the equivalent of one Angstrom of material thickness over an entire wafer.

In simple terms, by measuring the change in the wafer mass, variations can be detected on product wafers, and problems in the process can be identified very early on - saving valuable time, money and wafers. The technology is extremely reliable and cost effective, improving yield and reducing scrap with a low cost of ownership. The Mentor’s measurement technique is effective for all substrates, wafer sizes, wafer types and materials. It is non-destructive and compatible with product, test and blanket wafers.

The Mentor provides a family of reliable, low cost, high throughput, fully automatic mass determination tools with atomic layer repeatability for high volume manufacturing environments. Capable of throughputs of 60 wafers per hour, the Mentor tool has a small footprint of only 2 m² and provides nanotechnology mass measurement of product, test and blanket wafers independent of substrate size or material.

• Metryx has fully automated 300mm in-line metrology systems running volume production, and has been endorsed by major 200 mm and 300 mm fabs worldwide.
• Technology used is protected by international patents.
• Product designs comply with SEMI standards and industry standard components, and software protocols are used throughout.
• Multiple unit installations, running critical applications in fully automated production environments, have proven to be both reliable and cost effective.
• Key advantages include high throughput, low cost of ownership, independent of substrate, wafer size, wafer type and material.
• The measurement technique is also non-destructive and compatible with product, test and blanket wafers.

The Mentor is equipped with a standard equipment front end module (EFEM) housing an atmospheric robot within a mini-environment. The wafer handling capabilities of the tool rely on two front opening unified pods (FOUPs) located side by side at the front of the system. The tool is able to pre-identify the FOUP adaptors to achieve seamless handling.

The Mentor can also be configured to serve as a bridge tool in mixed wafer fab environments where 200 mm and 300 mm wafers are continually interchanged. For use as a bridge tool, one of the tool’s load-ports can be configured for 200 mm (either open cassette or SMIF) operation while the other remains at 300 mm.

If the semiconductor manufacturing process is made up of a series of steps that see material deposited and material etched or polished away, it follows that each of these steps will have an impact on the mass of any given wafer. That impact is an increase or decrease in the wafer’s mass. It then follows that by monitoring mass, we can accurately determine whether the deposition, etch or planarization process is working as it should or not. In theory, it sounds simple; it is a common sense approach to a very technical problem. In reality, Metryx has delivered a complex system that can determine process stability and performance more effectively and more cost-efficiently than any other solution on the market today.

Based on an ancient form of measurement, Metryx's Mentor technology is revolutionary in terms of the value it offers semiconductor manufacturers as an inline, on-product metrology tool. Simply put, being able to identify a process variation at the nanotech level as soon as it happens saves manufacturers a significant amount of money by reducing scrap and rework. As an inline tool, the Mentor offers a fast and reliable method to ensure a process is running correctly without having to wait for an offline tool, or losing a wafer to test. Further, the Mentor’s ability to be implemented following virtually any process step makes it one of the most versatile metrology tools on the market that is not restricted to use after selected process steps. As such, the Mentor can be incorporated in-line in virtually any area of the fab.

Over and above the technical advantages the Mentor brings to semiconductor manufacturing, it has been demonstrated to be commercially viable, rapidly increasing its adoption over the past 5 years, with follow-on orders accounting for fifty percent of its sales. In other words, once manufacturers use the Mentor in a manufacturing environment its value becomes quickly evident, leading to additional orders. The Mentor has proven its capabilities for advanced semiconductor manufacturing, as evidenced by its adoption in multiple leading 200 mm and 300 mm semiconductor manufacturing lines located around the world.

Metyrx are doubling revenues on an annual basis as our technology becomes more widely accepted in the IC manufacturing process. The basis of this growth is our Mentor technology and the capability that this technology provides our customers.

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Qcept Technologies
ChemetriQ 3000

The ChemetriQ 3000 provides rapid, full-wafer, inline detection of non-visual defects (NVDs). NVDs include both organic and inorganic residues, metallic contaminants, process-induced charge defects, as well as watermarks and other non-visual residue defects.

The ChemetriQ 3000 accomplishes this by employing an innovative, non-contact, non-destructive technology that detects work function variations on the surface of semiconductor wafers. These variations, which mark the presence of NVDs, are converted into image files using on-board software that can be easily ported to a fab's existing analytical tools for enhanced defect classification. The ChemetriQ 3000 is sensitive to 5E9 atoms/cm2 (one atom out of 200,000 per square centimetre), which exceeds the requirements outlined in the ITRS Roadmap for metallic contamination detection down to the 22-nm node.

Leveraging the ChemetriQ 3000, semiconductor manufacturers can reduce their yield loss through improved process monitoring, and achieve faster yield ramps through accelerated process optimization. For example, the

ChemetriQ 3000 detects NVDs non-destructively in four minutes compared to up to six hours with destructive analytical methods, making it ideally suited for inline process monitoring.

The ChemetriQ 3000 is highly complementary to today's existing optical inspection technologies, filling the inspection gap that exists today for a full-wafer, production solution that enables detection of NVDs.

As the missing link in moving the detection of NVDs to a highly automated inline process, the ChemetriQ 3000 enables chipmakers to broaden and expand their existing solution set to solve their NVD yield challenges.

As IC manufacturers integrate more new materials and processes into their manufacturing lines to improve the performance of their devices, process quality becomes ever-more critical to device yields. This is especially true with wafer cleaning and surface preparation, which are the most repeated process steps in the fab and among the most frequent sources of yield loss. The introduction of new materials has further narrowed the slim process margins associated with these processes, giving rise to NVDs.

In leading-edge semiconductor fabs, NVDs now account for as much as 30 percent of all defects. Since NVDs do not scatter light, they are undetectable by optical inspection systems. According to the latest edition of the ITRS Roadmap, the rapid sourcing of non-visual defects will become increasingly challenging-driving the need for affordable inspection techniques that go beyond optical microscopy and offer high resolution without sacrificing throughput. The ChemetriQ 3000 platform is the only inline wafer inspection solution that can detect NVDs.

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Sela
MC600i

The Sela MC600i achieves a fully automatic, reliable and rapid cross sectioning of wafer segments and dies. It is used to prepare samples, either for the analysis of defects, or to validate process steps. The area of interest is located and cross sectioned. Without further processing, the sample is ready for analysis on an SEM. It has dedicated software that enables automatic mapping and navigation to targets. It also features automatic off-loading for immediate inspection. Sela's MC600i has reduced the time required to locate and cross-section areas of interest from hours to less than 10 minutes with a fully automated process. The process is automated, and only basic training is required to use the system to obtain samples with no artifacts. Other than liquid nitrogen (usage is optional), absolutely no chemicals (not even water) are required by the process.

The microcleaving technology is patented and there are no systems available that cleave samples. Other methods used to produce samples involve sawing, grinding, polishing, or FIB milling - each requiring multiple machines and in-process inspections as the process approaches the target area. These are manual processes that require significant experience to achieve the desired results. Unlike micro cleaving, these methods create only one workable sample - one side of the sample is destroyed by the process. The MC600i produces two samples (each a mirror image of the other) for analysis. Worker safety is also improved because manual breaking of wafer segments is eliminated. Other benefits of the MC600i include high throughput (9 min/sample) and accuracy (less than 0.3 micron), superior cross-section quality, and it significantly reduces the diagnostic cycle for both failure analysis and process monitoring. Specification capabilities include cleaving of smaller wafer segments and dies as close of 0.5mm to a sample edge. High throughput (9 min/sample) High accuracy (less than 0.3 micron) Reduces time to look and cross-section the wafer(s) Able to get two samples for analysis from one cleave Artifact-free Chemical usage is not required Back to top

FEI Company
Helios NanoLab 400S

The Helios NanoLab series is the world's most advanced DualBeam platform for sample preparation, imaging and analysis in semiconductor failure analysis, process development and process control laboratories. All Helios NanoLab systems combine the innovative Elstar electron column for high-resolution, high-contrast imaging with the high-performance Sidewinder ion column for fast, precise cross sectioning. The advanced system design optimizes the column configuration to provide the best combined performance available in any dual beam (FIB/SEM) system. The Helios NanoLab 400S is optimized for high throughput, high-resolution S/TEM sample preparation, imaging and analysis. Its exclusive FlipStage and in-situ STEM detector can flip from sample preparation to STEM imaging in seconds without breaking vacuum or exposing the sample to the environment.

The FilpStage mounts on a five-axis motorized stage that accommodates samples up to 80 mm in diameter with full coverage and industry-leading repeatability. Samples up to 100 mm can be introduced through the load lock for optimal throughput. Larger samples may be introduced through the chamber door. Elstar Electron Column The innovative Elstar electron column, newly introduced in the Helios NanoLab series, provides the foundation of the systems' unprecedented high-resolution imaging capability. Helios NanoLab systems are capable of 0.8 nm STEM resolution. SEM resolution is equally impressive with 0.9 nm at optimal working distance and 1.0 nm at the DualBeam coincident point. Imaging performance is further enhanced by advanced scanning and through-the-lens signal detection systems that provide dramatic improvements in contrast and signal-to-noise ratio. Double magnetic shielding increases the systems' immunity to environmental fields. Constant power lens technology eliminates thermal instabilities caused by routine changes in lens power. Sidewinder Ion Column The Sidewinder ion column combines high-resolution with exceptional low voltage performance. Not only does it enable excellent ion image resolution (5 nm @ 30 kV, coincident WD), it also provides the most precise ion milling, helping to insure that valuable defect information is not destroyed by the cross sectioning operation. A full range of beam chemistry options supports accelerated milling, selective milling, deposition and enhanced imaging with both ion and electron beams.

Integrated Preparation, Imaging and Analysis
The Helios NanoLab 400S is the ideal platform for S/TEM sample preparation and imaging. The in-situ STEM detector permits real time monitoring of the STEM image while thinning, for ultimate control of the preparation process and localization. The Sidewinder ion column's ability to maintain small beam diameter at less than 1 kV enables low-energy, grazing-incidence final clean-up to remove surface damage induced by higher-energy milling. The 400S provides STEM capability at accelerating voltages up to 30 kV, or the sample may be transferred to a high voltage S/TEM for ultra high resolution imaging and analysis.

Extensive automation permits unattended preparation of multiple site-specific S/TEM samples in a single session at a cost-per-sample competitive with conventional SEM bulk sample preparations. Optional X-ray (EDS or WDS) spectrometers offer compositional analysis in thin samples with resolution down to 30 nm. Automated slice and view capability can acquire a sequence of cross sectional images and reconstruct a three-dimensional model of the cross-sectioned volume that can be viewed and virtually re-sectioned in any direction.

All bleeding-edge IC manufacturers developing new processes and introducing new materials at 65nm and below need the ability to accurately inspect and measure their product. In order to do this, R&D labs require the ability to cut into and inspect cross-sections of the finished product. An Ultra High Resolution DualBeam system (combining SEM and FIB) is required to accurately find, cut, and image these parts.

In some cases, the development and process engineers can get the data they need by looking at the surface of the cross-section using very low energy electron beam imaging. The Helios NanoLab 400S offers the highest resolution SEM column in a DualBeam at very low beam energies (down to <1kV) to enable engineers to get the best cross-section image possible with minimal sample damage. For more advanced structures that require higher resolution TEM imaging, the Helios NanoLab 400S is also the most advanced DualBeam available for creating high quality TEM lamellae. A thin lamella (in some cases less than 30nm thick) with minimal sidewall damage from FIB milling is required by the TEM to enable accurate structural and analytical results. The exclusive Flipstage and in-situ STEM detector combined with very low kV Sidewinder FIB milling on the Helios NanoLab 400S allow leading IC manufactures to create the best possible TEM samples which in turn enable faster, higher-yield process node shrinks.

The Helios NanoLab 400S has been adopted by nearly all leading and bleeding edge IC manufactures since its release in mid-2007.

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Mfg Vision
Floorvision yield management software

The FloorVision software tool provides faster resolution of semiconductor yield issues through integrated Yield Management, SPC (Statistical Process Control)and rapid root cause analysis. In FloorVision, customers have fab, wafer sort and test data linked seamlessly using genealogy.

Customers can manage product performance during characterization, yield ramp and volume production. Supply chain visibility and traceability of parts are improved. All reporting is dynamic, interactive and shareable with teams across the world in a secure environment. User-defined exception reporting automatically communicates product performance variances, increasing productivity and satisfaction levels amongst product engineers.

With its highly scalable configuration, this web 2.0-based data-management system integrates Manufacturing Execution Systems (MES) based reporting, genealogy, semiconductor fabrication, wafer probe and test data in a seamless flow across multiple geographies.

This means that engineers, managers and executives can accurately capture critical data, speedily determine the root cause of product failures, efficiently correlate failures to process parameters, and quickly disseminate thorough yield reports to team members and other key decision makers.

The result: reduced downtime from process failures, improved productivity for product and test engineers, and lower IT costs. Among the key attributes of the FloorVision tool are: extremely fast data processing (results are available to the user in seconds), ease of use (with a little training any customer employee, not just yield management experts, can be up and running with the tool), and stability (Floorvision tool is server based).

Feedback from multiple clients is that this yield management tool is "technically the best on the market". It combines leading edge features with the ability to analyze results virtually in real time. This provides customers the ability to increase productivity, lower IT costs and ultimately improve margins on their products.

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Virage Logic Corporation
Self-Test and Repair (STAR) Yield Accelerator

Virage Logic's Self-Test and Repair (STAR) Yield Accelerator, announced on October 22, 2007, is a new option available for the STAR Memory System, Virage Logic’s industry-leading embedded test and repair solution. The STAR Yield Accelerator provides a complete solution for automated silicon verification, vector generation, silicon analysis, and yield ramping of embedded memories. Integrated with the industry leading STAR Memory System embedded test and repair solution, the STAR Yield Accelerator bridges the design and manufacturing disciplines to enable automated test vector generation, silicon analysis, fault isolation and classification to be used at the critical semiconductor tape-out, bring-up and volume manufacturing stages, dramatically reducing silicon time-to-test, time-to-product bring-up, and time-to-volume production.

The STAR Yield Accelerator family of products consists of the STAR Verifier, STAR Vector Generator, STAR Debugger, and STAR Yield Analyzer, which can be licensed separately or in a package. Leveraging the infrastructure of the STAR Memory System, the STAR Yield Accelerator automatically generates vectors for test equipment and provides fault analysis and root-cause failure guidance based on silicon test results.

Virage Logic’s STAR Yield Accelerator has capabilities and benefits that address the needs of test, product, and process engineers using the STAR Memory System. Automation support for verification and vector generation provides value to all design and test engineers implementing the STAR Memory System for memory test and repair. Automation to easily enable silicon debug through embedded memories is an essential capability for test and product engineers to quickly and easily identify and isolation silicon related issues. Automation to aid in failure trend analysis is a value added capability for any company that is shipping high volume products or any silicon manufacturer that is producing a high volume of wafers. The ability to even incrementally improve yield can dramatically impact profitability.

The STAR Yield Accelerator is proven to dramatically reduce silicon time-to-test, time-to-product bring-up, and time-to-volume production. Through preliminary engagements with several key semiconductor customers at 90nm, 65nm, and 55nm process nodes, the STAR Yield Accelerator has demonstrated its ability to meet design requirements of integrated device manufacturers (IDM), fabless and foundry customers. The STAR Yield Accelerator rapidly, cost-effectively and accurately identifies, analyzes, isolates, and classifies memory faults as designs are readied for transition from first silicon to volume manufacturing. By automating this process within the existing development workflow, STAR Yield Accelerator works with the STAR Memory System to speed system-on-chip (SoC) time-to-volume and dramatically boost yield percentages. The STAR Yield Accelerator can reduce silicon bring-up by months, reducing overall time-to-volume production.

STAR Yield Accelerator’s verifier, vector generator, and debugger components automatically generate vectors for test equipment and provide fault analysis and root-cause failure guidance based on silicon test results. Using STAR Yield Accelerator, manufacturers can rapidly and directly analyze failures manifested in embedded memories and inspect the physical location and class of each fault to determine the root cause without involving the intellectual property (IP) vendor or SoC designers.

Offering capabilities far beyond conventional physical de-processing and manual analysis, the STAR Yield Accelerator can pinpoint the exact physical location of memory faults and provide guidance of the root cause. By enabling engineers to troubleshoot yield issues in a secure and efficient manner, the STAR Yield Accelerator protects both manufacturers’ sensitive process data and the designers’ closely guarded design data.

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Vistec Semiconductor Systems GmbH
LMS IPRO4

Vistec's LMS IPRO4 is a fully automated mask metrology system. It is capable to measure registration (overlay on reticles) as well as critical dimensions (CD) in transmitted light or in reflected light at i-line (365nm).

The LMS IPRO4 is designed to support mask metrology requirements of the 45nm node. The system is famous for its measurement performance and reliability, for its straight forward user interface and its comprehensive data evaluation software.

The LMS IPRO4 can be equipped with an optional 300mm wafer chuck in order to qualify thoroughly pattern placement of any wafer lithography tool, either scanners or direct write e-beam systems.

The system is equipped with a 904 nm infrared laser auto focus (LAF) diode. It is used in conjunction with a TV autofocus system for obtaining edge intensity profiles and ultimately edge locations in a quality that has not been possible ever before: Experimentally measured positions of structures as small as 0.13 micron showed excellent results.

Superb Mechanics:
One of the main assets of the LMS IPRO4 is the stage. The LMS IPRO4 measures up to a maximum of 300 mm in both the X and Y directions. The plate holders are constructed of a low expansion ceramic substance, and the optical head and other mechanical components are made from "Invar" - a low expansion metal.

Safe Substrate Handling:
The automatic substrate handling system with an eight position magazine allows you to temperature acclimate substrates in the environmental chamber prior to measurement. An optional SMIF package is available for particulate control. The SMIF system can handle 6025 reticles and is capable to rotate substrates in 4 different orientations. The integrated reticle flipping unit enables most convenient substrate handling. Manual SMIF pod opening even in case of measuring pelliclized reticles is redundantized.

Wafer substrates are loaded manually onto a loading station equipped with a wafer vacuum chuck. This chuck can then be placed automatically onto the measurement stage or into the eight position magazine for temperature acclimation or batch processing.

Automatic Operation:
You can program the batching of multiple measurement jobs on multiple substrates for automatic operation. The batch processing programming runs either on-line or off-line. The system can also be programmed in batch mode to automatically process measurement output results for input into Deva or LMSASCII according to pre-determined templates. With the LMSASCII software program you can output measurement results data in fully customizable formats and export them into other programs such as Microsoft Excel. Utilizing third party software users can remotely operate and/or monitor the LMS IPRO4 via network.

• Unique and highly innovative product
• Continuous adaptation to customer needs over many tool generations
• Measurement performance significantly better than specifications
• Reliability
• Smooth installation of beta-site system

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VLSI Standards, Inc.
NanoCD Standard

NanoCD Standard - The NanoCD (NCD) is the first commercially available standard to provide line width accuracy calibration at the 45 nm, 65 nm, 90 nm and 130 nm nodes (and 32 nm coming!). Use these standards for tool matching, calibrating the width of a CD-AFM tip, or CD-SEM diagnostics. The NanoCD consists of a small chip containing a single isolated line 4 mm long (3 mm certified), offering thousands of distinct measurement sites. Chips are fabricated at VLSI Standards using a patented technique that results in lines with high uniformity and low associated uncertainty, unachievable through conventional lithography methods. For compatibility with wafer handlers, the chip is mounted to an etched pocket of a silicon wafer carrier. Global alignment marks, rulers and pattern recognition features extending from the chip to the wafer ensure that the target is always located, and measurements can be repeated.

The width of the line, or the Critical Dimension (CD), is certified with TEM and is traceable to NIST and to the international system of units (SI) through the atomic lattice spacing of single crystal silicon.

Product Specifications
Nominal CD Values - 25 nm, 45 nm, 70 nm, or 110 nm.

Accuracy - 25 nm ± 0.5 nm, 45 nm ± 0.7 nm, 70 nm ± 0.7 nm, 110 ± 0.8 nm

Material of CD line

Amorphous Silicon

Length of Line - 3 mm certified

Defectivity of Line - 5% Max. (150 µm of total 3,000 µm)

Traceability - Traceable to the SI units through the atomic lattice spacing in the silicon crystal by TEM

SEMI Specification Silicon Wafers - 200 and 300 mm diameter wafers available in X or X,Y configuration.

This product has allowed for a vast improvement in the precision and matching of production CD-SEMs and has enabled the use of the CD-AFM for accurate linewidth measurement during process development and line monitoring, both in the wafer fab and in the mask shop. Prior to the release of NanoCD, the absolute accuracy of the CD-AFM linewidth metrology was limited to about 5 nm, which does not meet the ITRS roadmap requirement. The only available solution to accurate linewidth metrology was cross-section TEM, which is destructive, time-consuming, and expensive. With the use of the NanoCD, Critical Dimension metrology tools can exceed the ITRS requirements for linewidth metrology, in a fast, non-destructive, and inexpensive way. CD-SEMs have many critical system parameters that may unexpectedly change over time. These include beam size adjustment, auto focus precision adjustment, depth of field adjustment, astigmatism, electronic filtering algorithms, and tilt and columns tage alignment to name a few. The NanoCD Standard can be used on a daily basis to discover and diagnose these potential variables. With CD-AFMs, it is paramount that the user know the size and working condition of the probe tip being used on the instrument. With the NanoCD, the user can now measure the certified linewidth, and thereby calibrate the tip width. This ensures that the CD-AFM provides accurate measurements. The same calibration procedure is to be followed periodically, because the tip width changes over time due to wear. There are no commercially available competing products. The only alternative for accurate linewidth metrology is cross-section TEM. The NanoCD is also NIST-traceable, allowing users to meet quality system requirements. The certified lines have a high accuracy (<1 nm uncertainty), low line edge roughness, high contrast, and a large measurement area (4 mm in line length). The standard is available in various configurations such as wafer form for semiconductor & MEMS manufacturers, Mask form for photomask manufacturers and lithography concerns, and sample mounted for users of analytical instruments.

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ASM America, Inc.
Pulsar 3000 ALD Module

The Pulsar 3000 ALD module is a single wafer reactor that enables deposition of high-k materials for transistor and capacitor products. Atomic Layer Deposition (ALD) is a surface controlled layer by layer process for the deposition of thin films with atomic layer accuracy. The ALD process can be used to produce single or multiple layers of oxides, nitrides, or metals. The surface controlled growth mechanism provides excellent step coverage on aspect ratios as large as 100:1 with no pinholes. The Pulsar 3000 module is being used to deposit dielectric and metal films for DRAM trench and stacked capacitors, diffusion barrier layers for FeRAM, dielectric layers for magnetic head applications, and most recently, for dielectric and metal deposition in CMOS high-k/metal gate technology.

The Pulsar 3000 is a bridge tool capable of processing substrates from 150 mm to 300 mm in diameter. Multiple Pulsar 3000 modules can be integrated on a cluster platform and the modules can run either serially for extreme flexibility and complex stacked films, or in parallel for a high productivity solution for ALD deposition of a single film. Although ALD has been historically viewed as being a slow process, the Pulsar(r) 3000's unique delivery system and cross-flow reactor design has enabled development of high speed ALD processes with single reactor throughputs as high as 60 WPH for 100 A films. Futher more, the module is equipped with 6 sources capable of running solid, liquid and gaseous precursors. At a module footprint of less than 10 ft², the Pulsar 3000 is highly compact and flexible ALD system for research, development and high volume manufacturing. The Pulsar 3000 module is the first product to be used for high volume manufacturing of hafnium based high-k dielectrics for CMOS gate applications - enabling the first fundamental shift in material choice for the CMOS gate dielectric since the invention of the modern transistor.

The module has demonstrated long term manufacturability for the deposition of these new gate dielectrics. Defect performance is typically less than 10 adders @ 0.10 um and film thickness is controlled to less than 1 Angstrom range across a 300 mm wafer. The reactor is unaffected by invasive maintenance and does not require lengthy tuning runs or dummy wafers when processes are restarted after idle or maintenance. The Pulsar 3000 enables high-k gate dielectric deposition for replacement gate technologies and also enables uniform deposition of extremely thin capping layers (< 5 A) that allow use of high-k/metal gate technology in conventional gate first CMOS process flows. The capping layers can be deposited in-situ to eliminate any issues related to degradation of the high-k interface due to air breaks.

The Pulsar 3000 enables high-k dielectric deposition at low thermal budgets (< 400 C). This is particularly important for sensitive applications such as the CMOS gate dielectric, where PVD and other plasma based processes can result in film damage, and high temperature processes such as MOCVD can lead to interfacial layer thickening. The ALD process also provides the best film uniformity, purity and composition control for extremely thin film layers (<20 A). The Pulsar 3000 is the only high-k tool in production with HfCl4, a solid source. Use of halide based precursors eliminates the risk of carbon contamination in the dielectric, which has been proven to reduce the performance of these films. The reactor is a cross flow design, which is the best configuration for efficient purging of the reactor. The reactor design has been optimized to deliver laminar flow with minimal eddy currents and recirculation cells. This has resulted in a module with unrivalled defect performance and film uniformity, making the module a technology enabler for critical, yield sensitive applications such as the CMOS gate dielectric.

The module has the capability to run up to 6 sources (2 gases, 2 liquids, 2 solids) - resulting in a very flexible toolset for complex film stacks.

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Aviza Technology, Inc.
Versalis fxP-Integrated Process Solution for 3D-ICs

Aviza’s Versalis fxP system is a single wafer 200/300 mm cluster tool that integrates multiple processes (including etch, PVD and CVD) all on one platform. Targeted for advanced research and development (R&D) activities for 3D-IC devices, Versalis fxP offers a route for customers to develop their Through Silicon Via (TSV) technology and easily migrate their processes for high-volume production. This “one-stop shop” solution enables customers to save money by investing in less CapEx for R&D, minimize installation costs and make efficient use of fab area.

The Versalis fxP is based on Aviza’s production-proven single wafer platform. Its individual modules such as deep silicon etch, PVD and CVD have all been proven in high-volume manufacturing for various applications including wafer level packaging, MEMS and power semiconductors. Customers can benefit from Aviza’s process expertise in these areas in order to meet their stringent process specifications. For example, Aviza’s deep silicon etch is high rate, while Aviza’s PVD re-sputtering process has been developed to give the continuous via sidewall coverage needed for the plating step.

The Versalis fxP system allows R&D users to link processes in a way that would not be possible on traditionally configured single-process systems. On the Versalis fxP, users can link separate processes without breaking vacuum to discover potential performance benefits, and then apply those findings to optimally configure production tools.

Aviza sees 3D-ICs as a growth market to enable smaller factor devices (such as PCs, PDAs, mobile phones and other consumer products) with increased functionality and improved electrical performance. By leveraging the company’s process expertise in the areas of etch, PVD and CVD, we believe that Versalis fxP offers a unique solution to the R&D community focusing on 3D-ICs and TSV technology. On one platform, customers can develop their TSV processes in a cost-effective and efficient manner with the ability to seamlessly migrate these processes to the production environment. Packaging is a cost-driven activity and Versalis fxP significantly cuts R&D CapEx over traditionally configured single-use equipment. Aviza has already shipped a Versalis fxP tool carrying etch & CVD modules and is seeing significant interest for Versalis fxPs from Advanced Packaging houses, foundries and IDMs for the integration of etch, CVD & PVD technologies.

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EV Group (EVG)
EVG®150 NanoSpray Coating System

• Designed for fully-automated high topography spray coating.
• Patent pending spray coating technique for coating very small and deep patterns
• Unique spray process that is based on a spray mist created by ultrasonic nozzles
• Significant improvement in refined dispense and targeted positioning of the spray stream
• Supports wafers up to 300 mm diameter
• Homogenous coatings of features 300µm deep and 100µm diameter

The development of this novel system was driven by the emerging 3D Interconnect (3D IC) applications based on Silicon TSV (Through Silicon Via) technologies. This new milestone in photoresist application will enable users to carry out further lithography steps at the bottom of vias to create through wafer interconnects and allow a new bandwidth of applications throughout many technologies in Semiconductor processing markets. While the coating of vertical features is common practice in MEMS technology, it has also recently been adopted in emerging packaging applications based on TSV technology, used in the advanced packaging and interconnect arenas. Vias are used to interconnect the active front side of the wafer to the backside and further on to the pins of the specific wafer level package. This coating technology was first realized by EVG on their EVG100 series coating equipment by development and integration of new spray technology and techniques.

First systems have been installed at major customers and are being used to manufacture CMOS Imaging Sensor (CIS) packages based on TSV technology.

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MATECH
WaveEtch Advanced Wet Processing Tools

MATECH’s WaveEtch systems is unique because of the new capabilities they bring to the wet processing toolset of the semiconductor and photovoltaic industry.

These new capabilities include the ability to texture surfaces using wet processes, the ability to clean, thin, etch, and stress relief conventional as well as ultra-thin wafers (50 um and below), inherent single-sidedness, reduced chemical usage and reduced environmental impact. The WaveEtch systems can also wet process very thin wafers that are distorted or warped. All this wet processing power is embodied in a flexible, single tool capable of multiple processes and high throughput-up 1200 to 2400 substrates per hour. Substrates of virtually any size and shape can be easily processed by the WaveEtch systems.

The system’s LinearScan technology effectively eliminates virtually all transport-related and centrosymmetrical non-uniformities, which plague spin/spray or immersion processes.

At present, no commercial system provides these advanced capabilities in a single, cost efficient platform.

The WaveEtch LinearScan technology has also important applications in photovoltaic or solar cell manufacturing; from saw damage removal, to surface texturing for efficiency increase, to thinning the solar cell substrate.

The WaveEtch systems simplify the manufacturer’s toolset, lower chemical usage and its associated purchase and disposal costs, as well as often easing environmental regulatory compliance, resulting in overall production and costs of ownership (COO) reduction.

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Microcontrol Electronic srl
Photopolymer film lamination system

Leonardo 300 series, fully automatic bridge tool 200 – 300 mm system. Used to laminate permanent and not permanent photopolymer films in wafer level packaging and TSV processes. Used in MEMS application to create multilevel structures on silicon or any other substrates including glass and containing heavy topography or pre-etched features. All process parameters are fully controlled and loadable in recipes.

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Rudolph Technology
The NSX Series

The NSX Series is a high-throughput and repeatable macro defect inspection solution used throughout the device manufacturing process. Macro defects (defects 0.5 micron and larger) can be created during wafer manufacturing, probing, bumping, dicing, or by general handling, and can have a major impact on the quality of a microelectronic device. The NSX quickly and accurately detects yield-inhibiting defects, providing quality assurance and valuable process information. This information may be transferred to yield management programs, including Rudolph's DMS Decision software and fabwide DMSVision software for further analysis and review, reducing manufacturing costs and time to market.

Overview

• New NSX 100: High throughput inspection for 200 mm applications
• Automated, 100% advanced macro defect inspection
• Fast and consistent 2D bump inspection
• Provides process and defect information for enhanced process control and product consistency
• Features an easy-to-use Windows-based user interface
• Time-tested applications in semiconductor, optoelectronics, wafer bumping, data storage, micro electromechanical systems (MEMS) and micro display markets

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Alchimer
Electrografting process for TSV metallisation

Electrografting is Alchimer’s breakthrough proprietary process for the initiation and growth of thin films on conducting and semiconducting surfaces. It works by ‘grafting’ molecular precursors to a variety of materials, through creating covalent bonds between the materials.

Electrografting technology can be used to deposit copper seed layers in through silicon vias (TSVs), using a material called eG ViaCoat. Electrografting can produce conformal, ultra-thin, uniform and adherent copper seed layers in the 50 to 500nm range, even on resistive barriers. The production of such copper seed layers for high aspect ratio TSV metallization has been a major roadblock to 3D packaging adoption – PVD (physical vapor deposition) processes have already reached their limitations in terms of producing continuous layers for TSVs with aspect ratios of 3:1 and above.

Electrografting technology demonstrates continuous sidewall and bottom coverage even on highly scalloped TSV etch profiles, and at aggressive TSV aspect ratios. Reliable metallization of TSVs with aspect ratios of 13:1 is now possible.

Electrografting is a wet electrochemical process based on specific organic precursors. Because the size of the precursors being introduced is in the order of 0.5nm, it provides a method of depositing material at the scale required for leading edge process nodes, both today and in the future. The substrate is placed in contact with a wet solution and the process operates by applying a small electric current: due to the very nature of the molecular precursors and of the reaction mechanisms they can undergo, unusually small amounts of current - of the order of 1 to 10;A/cm2 - are enough to trigger the process uniformly at any point of the surface of the substrate. This is called the electro-initiation step, which involves electronic transfer from the surface to the adsorbed precursors at chemical bond distance.

Once the surface is “seeded” with adsorbed activated moieties, the same precursors can undergo alternative chemical reaction paths which lead to the formation of the desired layers: while the process is controlled by the electro-initiation step, subsequent steps immediately following the electro-initiation may involve purely chemical reactions depending on the nature of the molecular precursor. In any case, the electro-initiated nucleation secures the growth of the film in a conformal and uniform manner. Through controlling just the current, Alchimer is able to demonstrate the deposition of ultra thin films of less than 10nm, with high uniformity across surfaces over a broad range of substrate resistivities.

This process can easily be implemented using industry-standard copper electroplating equipment, removing any requirement for additional capital expenditure; the process has been demonstrated on existing high-end 12-inch tools all the way down to legacy 6- or 8-inch equipment. The process is also compatible with CMP and other post-processing steps required for chip packaging.

Electrografting is compatible with standard barrier materials, including, but not limited to, PVD, CVD and ALD deposited Ta, TaN, Ti, TiN, WN, Ru and bi-layers. Alchimer has 25 patents and patent applications pertaining to this technology.

PVD (physical vapor deposition) processes have already reached their limitations in terms of producing continuous layers for through silicon vias with aspect ratios of 3:1 and above. In practice, this is a major roadblock to the adoption of advanced 3D packaging.

Electrografting demonstrates conformal sidewall and bottom coverage even on highly scalloped TSV etch profiles, and at aggressive TSV aspect ratios. Reliable metallization of TSVs with aspect ratios of 13:1 is now possible.

Electrografting enables significant reductions in cost of ownership (CoO) compared to dry vacuum processes. For example, for 10:1 aspect ratio TSVs, the CoO of Alchimer’s electrografting process is 85% less than that of a traditional PVD process. The cost advantage increases further at higher aspect.

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FSI International, Inc.
ZETA Spray Cleaning System with ViPR Technology

The ZETA Spray Cleaning Systems are sophisticated surface conditioning systems that remove unwanted films and contaminants from the surface of semiconductor wafers at various stages in the microelectronic device fabrication process. Wafers are processed in multiple cassettes on a turntable inside the system's process chamber. As the turntable rotates, dispense jets spray the desired chemistry to the wafers' surfaces to dissolve and remove the undesirable films and contaminants. After chemical treatment, deionized (DI) water is sprayed on the wafer surfaces to rinse away the chemicals. Multiple chemistry and rinse steps may be employed depending on the customer's specific application. The process sequence is completed by dispensing high flow nitrogen through separate jets to dry the wafers and the processing chamber. Our control system and chemical mixing manifold allow the user to define, control and monitor a variety of chemical mixtures, temperatures and sequences.

FSI ZETA Spray Cleaning Systems with ViPR Technology delivers the highest performance, lowest cost solution for wet chemical material removal, including ashless photoresist stripping and residual metal cleanup after salicide processes. With on-wafer temperatures exceeding 200°C, ViPR technology maximizes chemical reactivity at the wafer surface to achieve the fastest stripping performance with the least film loss or damage to other materials.

ViPR technology's unique ability to maximize chemical reactivity at the wafer surface provides breakthrough improvements across a wide spectrum of front-end wet processing applications, including Co, Ni and NiPt etch for salicide formation, PR strip and post-ash clean, and wafer reclaim. The combination of fast, aggressive stripping with minimum effect on other materials is particularly important for advanced processes that use shallower implants and thinner films. For photoresist stripping, ViPR Technology eliminates the ashing step for all but the highest implant doses, reducing capital cost, footprint, processing time and process complexity. After salicide processes, including advanced low temperature NiPt processes, ViPR Technology effectively removes unreacted metal without attacking the silicide. Ashless photoresist and effective removal of residual metals following salicide are critical enabling technologies for today's most advanced processes. ZETA's VIPR technology enables these applications and increases productivity, reduces capital and operating costs, and improves process yields contributing directly to more profitable manufacturing operations.

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Nova Measuring Instruments Ltd.
NovaScan 3090Next

NovaScan 3090Next leverages a combination of Spectroscopic, Reflectrometry and Optical Scatterometry technologies in tandem with Nova's proprietary productivity tools to deliver the market's most advanced solution for High Volume Manufacturing (HVM) environments. Nova offers both a standalone platform - NovaScan 3090Next SA, and integrated metrology systems - NovaScan 3090Next IM. Optical CD & Shape Profiling: NovaScan 3090Next SA standalone platform provides a state-of-the-art metrology solution, implementing polarized normal incidence spectroscopic scatterometry with an extended UV and IR spectral range. Featuring the highest fleet-matching (tool-to-tool) and throughput, the NovaScan standalone platform is an ideal metrology solution for the most demanding 2D, 3D, and in-die Optical CD and shape profiling applications down to 32 nm.

High-end metrology meets 32 nm requirements

Best fleet-matching with no need for recipe adjustment or calibration

Unmatched throughput and reliability results in lower CoO

Full compatibility with Nova's IM platform enables a mixed solution

With NovaMARS, provides advanced 2D/3D and in-die modeling & measurement

Offers a wide range of metrology solutions for Etch, Lithography, CMP and CVD

NovaScan 3090Next IM integrated metrology platform provides a state-of-the-art metrology solution, implementing polarized normal incidence spectroscopic scatterometry with an extended UV and IR spectral range. Featuring the highest fleet (tool-to-tool) matching and throughput, the NovaScan integrated platform is an ideal, cost-effective metrology solution for the most demanding 2D, 3D, and in-die Optical CD and shape profiling applications down to 32 nm.

High-end metrology and APC enabler down to 32nm

Best fleet-matching with no need for recipe adjustment or calibration

Unmatched throughput and reliability results in lower CoO

Full compatibility with Nova's SA platform enables a mixed solution

With NovaMARS, provides advanced 2D/3D and in-die modeling & measurement

Offers a wide range of metrology solutions for Etch, Lithography and CMP

Challenges of Optical CD & Shape Profiling

As design rules shrink to 65 nm and below, CD measurements are no longer enough to determine device characteristics and ensure performance. New metrology challenges demand measurement of the full profile of a structure such as height, depth, and sidewall angle (SWA) of vertical profiles, foot, notch, high aspect ratio contacts, and more.

As the correlation between test structures and in-device parameters deteriorates, the need for in-die measurement capabilities increases.

Shrinking process windows dictate similar shrinkage of the Total Metrology Uncertainty (TMU), making high precision and fleet (tool-to-tool) matching a critical requirement for metrology solutions, while maintaining high throughput and low Cost of Ownership. Optical CD solutions are widely used in Etch, Lithography, CMP and CVD, in many cases to replace CDSEM systems.

Nova's Solutions for Optical CD & Shape Profiling
NovaScan 3090Next metrology systems, based on patented normal incidence spectroscopic scatterometry, provide full Optical CD and shape profiling for 2D and 3D structures on test pads and in-die. Nova's metrology products feature industry-leading fleet (tool-to-tool) matching and the highest throughput, providing both Stand-Alone (SA) and Integrated Metrology (IM) Optical CD and shape profiling solutions for technology nodes down to 32nm. Both SA and IM architectures are fully compatible in recipe transferability and fleet matching.

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Replisaurus
ElectroChemical Pattern Replication ECPR

Replisaurus’ advanced metallization technology targets micro and nanoscale metal structures used for applications within microelectronics, optoelectronics, sensors, flat panel displays and advanced circuit boards. Replisaurus’ ECPR technology redefines the fundamentals of micro and nanoscale metallization and delivers a metallization process with superior performance/cost ratio.

The integrated “ElectroChemical Pattern Replication” (ECPR) process is an enabling technology targeted at key growth markets such as integrated passives, copper pillars and 3D integration (TSV). The company has demonstrated fine pitch/high resolution capability (&#8804;280nm space) and significantly improved thickness uniformity. The Replisaurus process offers a simple and cost effective integrated solution eliminating several traditional process steps thereby reducing complexity. The number of process steps in a typical metallization flow are reduced from eight (8) to three (3), resulting in shorter cycles times and a simplified production flow.

ECPR is a fab friendly, environmentally clean process which does not use any solvents, developers or strippers and has extremely fast plating rates. The ECPR technology is a “Design Enabling” technology for integrated passives enabling advanced designs, eliminating the need for prototyping and dummy plating patterns. The electrochemical replication principle of ECPR combines the precision and resolution of advanced lithography with the ease and efficiency of electrochemical deposition into one single integrated process solution.

Consequently, ECPR is a clean technology which significantly reduces costs for equipment, maintenance, personnel, clean room, and direct materials as well as provides high throughput capabilities due to its cycletime efficiency. Replisaurus Technologies offers complete production solutions including IP enabled equipment, replication templates (masters), chemicals and technology transfer.

Competitive Advantages
The principle of direct metal depositon using ECPR delivers a number of competitive advantages in performance, cost of metallization and environmentally clean technology.

Customer Value Proposition
Compared to conventional lithography-based metallization ECPR offers:

1. Improved device performance and process control
a. Improved metal thickness uniformity, without pattern dependent variations that are inherently associated with through mask plating.
b. Low resistivity metal with very high purity.
c. Minimum line width variations and well controlled conductor profiles.
d. Short process cycles with fast process performance feedback.

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Solvay Fluor
F2 mixture from Solvay Fluor for chamber cleaning

Solvay Fluor can deliver worldwide F2 mixtures in cylinders. The Fraunhofer Institute in Munich has tested this gas mixture as cleaning agent, demonstrating its superior performance over the actual cleaning recipes on an AMAT P500 tool. The F2 mixture is relatively easy to handle, provided that the right passivation procedure is carried out before utilization. A single passivation procedure assures the reliability of the delivery system for ever. All necessary equipments (mass flow controllers, gaskets etc...) are already available on the market; it was possible to set up the facility in short time and with comparable costs with an NF3 delivery system. The tests have shown how the F2 mixtures clean faster than NF3 and CF4 recipes. In particular, the NF3 recipe requires 60 sec to etch 1 micron SiO2 layer, whilst F2 mixture needs only 47 sec. This means a throughput advantage of the 21%. The usage of material too is reduced, while the above mentioned performance is obtained with 0,24gr of F2, whilst one needs the double amount of NF3. This has a consequence not only on costs, but also on the environmental balance of the process because F2 has GWP=0 and it is easy to abate. The AMAT P5000 tool did not show any compatibility problem with the new mixture. The particles generated during the cleaning process are in line with the industrial standard and similar for any recipes.

• Best throughput cleaning mixture
• Low gas consumption
• Low process environmental impact
• Ease of implementation and industrial application

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Surface Technology Systems plc
Pegasus DRIE technology for 3D packaging applications

Building on over a decade's experience in deep reactive ion etching (DRIE) of silicon for MEMS manufacturing, STS latest DRIE system, named "Pegasus", has proved to be a successful, enabling plasma etch tool not only in the MEMS industry but also in through silicon via (TSV) etching in emerging advanced 3D-IC packaging applications.

Launched in September 2005, STS’ Pegasus system utilizes the “Bosch Process” which is a well established method of anisotropically etching deep, high aspect ratio features into silicon, switching between a passivating C4F8 plasma and a reactive SF6 plasma. This dry plasma process offers significant advantages over the competing laser drilling technique, particularly when via holes are <10um and via hole densities are high. Pegasus has a unique plasma source design which offers market-leading silicon etch rates, typically 30% faster than conventional de-coupled "high rate" plasma sources. This high etch rate increases throughput, reducing cost per die. Another important factors when etching very deep features such as via holes into silicon is that conventional DRIE sources tend to have non-uniform plasma characteristics across the wafer, which can lead to feature tilting and a corresponding reduction in device yield, particularly for large diameter wafers typically used in 3D packaging applications. Pegasus has been designed in such a way to minimize this effect by careful control of the plasma conditions (including ions, electrons and radicals) across the whole wafer surface.

Another undesirable characteristic of the Bosch Process is the “scalloping” of the via sidewall, caused by the isotropic nature of each short SF6 etch step. The shorter the etch step, the smaller the “scallop” - giving smoother sidewalls. Sidewall roughness should be minimised in TSV etching because a rough sidewall could cause problems with subsequent via hole filling steps. STS’ Pegasus system minimizes sidewall roughness through a combination of hardware and software features which allow very fast switching between the passivating and etch plasmas. This means that each individual etch step can be very short, giving smooth sidewalls without reducing the total etch time, and consequently the overall etch rate is not adversely affected.

Pegasus has now proved itself to be a commercially successful product, with an installed base of over 65 plasma chambers sold in less than 3 years. Many of the systems have been multi-chamber cluster tools for high volume manufacturing applications.

With its high silicon etch rate, control of plasma uniformity and fast plasma switching capabilities, Pegasus offers truly enabling capabilities to companies investigating new ways of packaging devices using through silicon via etching in 3D-IC / wafer-stacking applications. Coupled with industry-standard Brooks handling cluster platforms, the Pegasus provides these market-leading process capabilities with production-proven wafer handling, all combining to reduce cost per die for the final end product.

The Pegasus tool has been a significant step in STS’ continual development of their DRIE capabilities, and with the experience gained during the development of Pegasus and improving the technology, the focus now moves to processing larger (300mm) wafers to meet the requirements of the packaging industry as they move to full scale implementation of 3D/TSV-based solutions.

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Agilent Technologies
The 4080 series of Parametric Test Systems

www.agilent.com

This new family of test systems is a superset of the previous 4070 series of test systems which combines the proven accuracy and reliability of the previous generation with significantly higher throughput.

The 4080 is already well proven in several major semiconductor companies where it is in manufacturing use on a 24 * 7 basis.

Existing and new wafer fabs running advanced processes face ever-greater parametric testing challenges. Out of necessity, parametric test has expanded beyond pure DC measurement and now spans a variety of different measurement types, including parallel test, Flash cell write/erase testing, and RF S-parameter characterization. Anticipating these needs, Agilent has developed the versatile and flexible 4080 parametric test platform.

Next generation test platform boosts performance with ultra-fast CPU

The newly-designed 4080 platform incorporates a more powerful CPU and other architecture improvements that boost the throughput of transferred 4070 plans by 10 to 20 percent without any program modifications. This reduces test times and saves you money.

Virtual Multiple Testhead Technology offers dramatic throughput improvements All 4080 Series testers running SPECS support both synchronous and asynchronous parallel test using Agilent's Virtual Multiple Testhead Technology. Using this technique in conjunction with the appropriate test element group (TEG) design, it is possible to get throughput improvements of up to 50% over conventional serial techniques.

Flexible configuration minimizes costs 4080 Series testers are available in two versions: standard low-current and ultra-low current, allowing you to select the most cost-effective configuration for each 4080 Series tester that you purchase.

High-speed capacitance measurement reduces test times 4080 Series testers all support an optional high-speed capacitance measurement unit (HS-CMU) that is integrated into the test head electronics.

HV-SPGU supports testing of next-generation Flash memory cell processes

The 4082F and 4083A both support a Semiconductor Pulse Generator Unit (SPGU) mainframe and high-voltage SPGU (HV-SPGU) modules that permit testing of advanced Flash memory cell technologies.

RF S-parameter measurement and optional RF matrix permit efficient testing of RF structures in production

The 4083A supports an Agilent PNA for 20 GHz S-parameter measurements.

In addition, an 8x10 RF matrix option with 20 GHz bandwidth is also available to enable the test of up to 5 RF test structures in a single touchdown.

Uniform hardware platform protects your investment

All members of the 4080 Series share the same hardware, and it is easy to upgrade from one model to another. This protects your investment and insures that your equipment does not become obsolete.

Conformance to SEMI standards facilitates test automation

SPECS-FA, the factory automation version of Agilent's SPECS test shell, runs on all models of the 4080 Series tester family. SPECS-FA fully supports SEMI automation standards E5 (SECS II), E30 (GEM), E87 (CMS), E39 (OSS), E40 (PMS), E90 (STS), and E94 (CJM).

Linux OS improves supportability and lowers costs

The Agilent 4080 Series system software and Agilent SPECS and SPECS-FA test shells use the Linux operating system. This saves money through the use of cheaper and more maintainable Linux-based system hardware.

This system allows customers to seamlessly move from older platform to the newer platform whilst retaining existing test code resulting in hassle free deployment.

System has new features which allows on wafer S parameter measurements through an RF switching matrix plus the ability to test NVM structures at up to +/- 40V via the SPGU with arbitrary waveform generator.

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F&K Delvotec Bondtechnik GmbH
G5 Wirebonder

F&K Delvotec’s fifth generation Wire Bonder 64/66000 G5 is used to connect semiconductor chips to their substrate using ultrasonic energy to weld the wires. The flexible machine base can be fitted with different bond heads for quick changeover from fine to heavy wire applications and even from fine to heavy ribbon applications. The specialised HARB (Heavy Aluminium Ribbon Bonding) capability processes aluminium ribbon for power applications. This technology has gained popularity over the last few years because it features higher current carrying power on a smaller contact area while simultaneously increasing bonding productivity. Nonetheless as with all other versions of the G5 system the bond process remains robust and reliable and the patented Bond Process Control BPC can be employed to improve process quality. The G5 systems accuracy is 10µm @ 3 sigma;. The wire bonder can be equipped with a manual work station or custom-tailored automatic part handling for high-volume production environments to master even the most demanding applications. The system comes with an optional integrated Post-Bond inspection system, which allows for 100% quality check on the entire production volume without compromising throughput. The G5 modular design ensures not only low equipment cost but also conserves valuable floor space.

One machine base with different bond heads for easy and quick changeover of fine, heavy and ribbon.

High Accuracy: 10µm @ 3 sigma

Very low cost of ownership.

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HÜTTINGER Elektronik GmbH + Co. KG
HMP - DC Power Supplies

HMP - DC Power Supplies that are for High Power Impulse Magnetron Sputtering (HIPIMS). The HMP is ideally suited and functional for semiconductor applications due to its high metal atoms ionization effects.

The HMP’s main attributes focus on extreme preciseness to trench filling in order to create an astonishing adhesion demanded by today’s most modern industrial processes. The HMP enables the formation of deposits by highly - ionized metal atoms in effect gaining hard films with much higher qualities and becoming ‘droplet - free’. Furthermore, it permits the production of exceptionally durable and resilient surfaces. The HMP product is an unequalled combination of improved carbon protection against corrosion with an extraordinarily wide range of applications featuring extremely precise, smooth coating and hardening. The most important features which provide sophisticated benefits in using this technology are: - High ionization of sputtered material of HMP enable superior controllable coating features (adhesion, uniformity, porosity, hardness).

- Ionized material can be directed for anisotropic processes (give precision to trench filling) HMP is designed to support processes like surface coating and etching.

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Kulicke & Soffa Industries
The IConnPS High Performance Wire Bonder

The IConnPS High Performance Wire Bonder offers advanced features, and process capabilities for wire bonding the latest stacked die, Low K, and multi-tiered packages. Many new features will assist customers increase the efficiency and productivity in their factories.

Offering +/- 2.0um accuracy for sub-35um ultra fine pitch requirements, the wire bonder features advanced looping processes, automatic self-teaching Bond Integrity Test System (Auto BITS), and programmable focus optics for complex stacked die packages. Its advanced Servo Control System is an enabler for more sophisticated looping, adding the ability to make both more and finer adjustments and lower loop profiles that enable thinner packages which in-turn enable smaller and thinner end products. IConnPS has a larger Bondable Area - a full 80mm, which enables the bonding of lead frame strips and substrates in larger formats for greater productivity throughout package assembly. An advanced motion control system, along with the fastest vision processor and camera system available, enable the IConnPS to provide the most throughput of any wire bonder in its market. A new improved Menu System called Pro-Loop simplifies the teaching process when using more complex loops. It is an example how the IConnPS remains easy to use while offering more sophisticated processes. The IConnPS High Performance Wire Bonder sets a new standard for IC inter-Connect performance with advanced features that address the need for greater accuracy demanded by the latest and future packaging technology. Incorporating the industry's most powerful X, Y, Z motion control system, the IConnPS is the fastest bonder in its respective market. A large bondable area - 56 mm in the X and 80 mm in the Y direction - enables customers to design lead frame strips and substrates in larger formats. More devices per strip will mean more devices are processed with less material handling actions, resulting in better efficiencies throughout assembly.

A larger bond area is also important because it allows the rest of package assembly to optimize their processes around a larger strip form factor. When combining the bond area, with an accuracy of +/- 2.0 microns, and the raw speed of the bonder, which is 10% faster than the current world-leading Maxum Ultra, the combination results in higher UPH and MTBA for optimum net productivity and greater cost-of-ownership.

The IConnPS also offers two new premium loop processes - which are special ball bond looping profiles. The Advanced Loop allows process engineers to add more kinking motions during wire payout, which adds strength and stability for longer wires. This also results in less loop height variation, consistent knee bends over the edge of the die, and optimal approach angle to second bond. The Low Loop was developed for long, low, inboard, forward loops that need to stay under a maximum height of 50um from the top of the die - this is particularly important in thin stacked die and memory packages.

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Tokyo Electron Ltd
Precio automated wafer prober

Precio was designed to lower overall test cell operating costs while providing maximum flexibility for these demanding market requirements. Precio contributes to lower operating costs beyond the prober in areas such as tooling and probe card costs, labor, spares, and overhead. Precio maintains XY contact accuracy while enabling precision Z contact accuracy and control to stabilize contact resistance. It offers a new patented option for improved planarity between the chuck top and probe card, a critical requirement for optimized testing in high multisite and full wafer testing applications. Precio also offers inline high speed probe mark inspection capability, TELPADS-I, to drastically improve inspection functionality and throughput.

Applications Small Die and Fine Pitch probing Low-noise parametric probing High pin count and High multi-site SOC and Memory Full Wafer testing Features High productivity Small footprint High reliability Better Contact / Better Yield Short Lead Time TELPADS-I (Option) Auto leveling (Option) Back to top

Hesse-Knipps, Inc.
Multi-dimensional Control System

Implemented at the back-end of semiconductor assembly during wire bonding, the Process Integrated Quality Control system (PiQC) is a thorough, multi-dimensional control system that monitors the most significant bonding process values for judging bond quality. These measures can include mechanical oscillation, transducer current, wire deformation, resonance frequency and the scrub behavior during the welding process. It acquires data in parallel to the bond process to avoid impact on machine throughput, offering a real-time 100% quality control. PiQC records all relevant signals from a transducer integrated sensor and ultrasonic generator. A sensor was added in the transducer to provide all relevant feedback data for calculating a bond quality value. Values are recorded real-time and statistically analyzed based on a newly developed mathematical decision model. PiQC allows derivation of extensive quality statements. Signal feedback and processing allows detailed analysis of the welding process and translation into a quasi-optimized reference process. The quality control system calculates a quality index for each bond based on the actual feedback signal from the process. After the learning phase, PiQC can recognize any deviations in real-time, which can be classified and interpreted by an operator. Signal deviations can be linked to certain failure modes, enabling process specialists to react faster on problems.

Current methods of monitoring wire bond quality for both heavy and fine wire applications fall short of finding 100% of all failure modes. Monitoring the most applicable and significant measures for inspecting bond quality, PiQC addresses these limitations by relying only on actual data, without statistical assumptions. For the first time, all physically relevant measures are evaluated in real-time with an individual quality index for results. And unlike other process control methods, PiQC acquires data during the bond process, allowing for a throughput neutral 100% quality control.

After a learning phase, PiQC can recognize any deviation in real-time that can be classified and interpreted by an operator. It is possible to directly link signal deviations to specific failure modes. The user is presented with a maximum amount of information to ensure optimized process control. No other quality control system on the market offers such a potential in the bandwidth of acquired measurement signals as well as in the evaluation of these measurements.

PiQC offers a new definition of possibility in quality control, especially for companies with high and fast increasing quality demands. Once implemented, existing mechanical non-destructive tests may become obsolete.

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Nanoplas
HDRF - dry cleaning for advanced 3D silicon integration technologies

Nanoplas is a French start-up company that has developed a new process called HDRF , providing the ultimate in dry cleaning for advanced 3D silicon integration technologies.

HDRF - High Density Radical Flux - technology is based upon a proprietary ICP plasma source that makes it possible to produce 50 to 100 times more active species than competitive systems and eliminate plasma-induced damages. For the first time in plasma processing, samples are not exposed to electrical charges; substrates are processed in a “soft” high density flux of neutrals that is ideally suited for the new generation of embedded technologies.

Nanoplas’s current target application is advanced flip chip activation and isotropic etching for MEMS dry release, but the variety of available chemistries and process settings offers flexibility for many new applications. Additional competitive advantages include a high throughput, small footprint, and low COO at a low initial cost. Nanoplas is already enjoying rapid market acceptance, with orders received from large players in the UK, US, and Japan. The company expects to ship 10 to 15 systems this year and to reach over $10 Million in sales within 3 years.

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phoenix|x-ray Systems + Services GmbH
x|act - µAXI with highest defect coverage

Quality comes first in printed circuit board assembly. The new µAXI platform including the x|act software from phoenix|x-ray is an ideal solution for automatic solder joint inspection in your production. To achieve maximum defect coverage, µAXI is using micrometer resolution and highest magnification of details. phoenix|x-ray provides calibrated high precision offline AXI systems including the unique x|act software package for fast and easy CAD based fully automated inspection of solder joints. Small field of views with micrometer resolution, 360° rotation and oblique viewing up to 70° ensure to meet highest quality standards. x|act is a specifically designed, intuitive inspection program, which requires only a simple, one-time configuration. The component\'s CAD-data is read into the X-ray system and laid over the image (live CAD-overlay). This allows the user to have the complete sample data available at all times, even when using oblique views (tilt and rotation).

To minimise programming time x|act is using CAD import. Filters can be used to extract the required information out of customised data formats. The standard data format used with x|act is the neutral data format (ndf) which contains information about the position and size of component pads.

For ease of use the software works with pad-based information. The operator can link specific inspection strategies to each type of pad. Different pad types usually require different strategies. If a strategy needs to be changed in an existing program this can easily be performed by marking all pads of the same type and generating a new link to the new inspection strategy.

After import of the data the software automatically generates the inspection views. The programs can be generated off-line and are portable to all inspection systems of the same type, which saves time and money.

x|act software runs on standard phoenix|x-ray microfocus systems using calibrated high-precision CNC manipulation. The system is using a unique local 3D height and distortion referencing method. Highest precision is achieved by measuring as many fiducials as required. By using X-rays instead of optical triangulation sensors the method does not depend on the quality and reflectivity of board surfaces. The image chain is calibrated and any distortion is automatically compensated. The combination of all these efforts allows for maximised positioning accuracy of just a few microns even at oblique viewing (70°) and rotation (360°).

The software provides a LIVE overlay of the X-ray image and the CAD information. This overlay is available even for oblique views. The pad ID is visible at any time. In addition, the pad specific inspection results are accessible by mouse click.

Even if the system is used for manual inspection only the CAD overlay is very beneficial, because it allows easiest pad identification. The overlay technique is extremely convenient for the operator due to perfect orientation at any time (reliable identification of a specific joint or a specific group of joints on a board with thousands of solder joints can be time consuming).

Microfocus and nanofocus X-ray inspection allows evaluating the quality of all usual solder joints. Any feature caused by the soldering process may be detected, as far as it has an influence on the shape of the soldered connection. Most defects can also be detected fully automatic, whereby the line throughput may limit the test depth.

As a unique new solution for µAXI with highest defect coverage and minimised false call rate, phoenix|x-ray's automated software platform x|act meets even future zero defect quality standards. Outstanding image quality, highest magnification, maximised position accuracy, easy CAD based offline programming, full program portability, and CAD-data overlay even in rotated and oblique live views ensure ease of use and highest product reliability. The great versatility makes the microme|x with phoenix|x-ray's x|act software package the new inspection solution of choice for zero defect µAXI as well as full 3D CT of a wide range of quality-sensitive electronic assemblies.

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SET
Kadett device bonder

The KADETT high-accuracy placement and bonding system fits R&D laboratories and pre-production environments with semi-automatic operation and a flexible platform accepting a range of substrates. The machine comprises a pick-and-place function and bonding processes including in situ reflow, thermo-compression, and thermo-sonic and adhesive bonding with forces up to 75N. The ±3μm alignment is directed by a vision system with independent, high-resolution video microscopes on the chip and substrate, and a 0.1µm resolution x/y alignment stage.   Back to top

Hach Ultra
ORBISPEHERE 510

The ORBISPHERE 510 instrument with the capability of connecting TC sensors for process control monitoring. The instrument offers multi-channel capability for both thermal conductivity sensors measuring H2 or N2 and for electrochemical sensors measuring O2. This complete system is designed for process monitoring in liquid or gas phases across a wide range of applications for the electronics industry.

Improved accuracy coupled with fast response time is a key process control attribute for advanced semiconductor processing.

Up to 3 sensors using electrochemical or thermal conductivity technologies reduces cost of installation and ownership, according to the company.

A high level of accuracy, rapid response time and selective gas measurements are claimed to give reliable and effective process monitoring. Software is accessible through a full colour touch-screen allowing easy configuration of the instrument for process parameters and alarms. The main window displays real time process readings, graphed sensor trends, alarm limits, temperature and event occurrence. This complete system is designed for process monitoring in liquid or gas phases across a wide range of applications.

To assist with process investigations, data can be easily transferred using one of the digital communication standard protocols such as RS 485, Ethernet, USB or Profibus DP in addition to traditional analog outputs. The ORBISPERE 510 provides efficient 3-in-1 process monitoring, process efficiency and minimized total cost of operation, according to the company.

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HORIBA Jobin Yvon SAS
Simple Thin Film Measurement with the Auto SE

The Auto SE is an innovative new thin film measurement tool for determining the thicknesses and optical constants (n,k) of thin layers and multi layers. The instrument has been introduced by HORIBA Jobin Yvon to simplify thin film analysis whilst maintaining the major advantages of ellipsometry such as non-destructive analysis, accurate thickness measurement with angström resolution, and multi-layer measurement capability.

The Auto SE covers the diversity of thin film applications, in the fields of thin film photovoltaics, micro-electronics, flat panel displays, functional and optical coatings and biotechnology.

The Auto SE is an integrated compact system that guarantees efficiency and productivity for routine analysis of thin films. Its design combines automation with experimental modularity.

The instrument includes a 200x200 mm sample stage motorized in the XYZ axes for automatic loading and alignment of the sample. XY horizontal translation allows mapping of thin film uniformity over the sample area. Each point on the wafer map is measured in less than 1 second, with full spectral information available over the range 440 - 850nm.

The Auto SE features real-time visualization of the measurement site and automated selection of 8 spot sizes. This is very useful for cases where the sample is patterned or has poor surface quality. In these cases the user may view exactly where the sample spot is located using the Vision System, and choose the optimum spot size accordingly.

The patented MyAutoView Vision System is mounted within the standard ellipsometer optics. This unique design provides two main advantages:

- Visualization of the measurement site for all kinds of sample

- Selection and measurement of only the front reflection for transparent substrates

The image provided has a field of view of approximately 1mm² and a resolution of 10 µm.

The Auto SE also offers a large choice of accessories (such as temperature controlled cell, luiqd cell, 360° rotation control, autosampler, plastic film mount, etc...) to accommodate a wide range of experiments and sample shapes.

The Auto SE is controlled by the AutoSoft software integrated into the common software platform that controls all HORIBA Jobin Yvon ellipsometers. AutoSoft integrates very intuitive interfaces allowing full automatic analysis of thin film samples with simple push button operation.

Sample analysis takes only a few seconds and provides a complete report of film thicknesses, optical constants, surface roughness, and film inhomogeneities.

As the software is Multilanguage it is simple to operate for everyone.

The software was created to fit the needs of three types of users:

- OPERATOR using a simple interface for routine thin film control

- ENGINEER with a large variety of analysis functions to optimize results and/or experimental recipes

- SERVICE with an interface for detection and diagnosis of possible problems of the system; thanks to built-in diagnosic indicators including in Auto SE.

The Auto SE is a new generation of thin film measurement tool that combines ease-of-use with the accuracy of spectroscopic ellipsometry. The Auto SE is a turnkey system that is ideal for the quality control laboratory and for industrial lines that need routine thin film measurement.

Unique Evolution of the current Spectroscopic Ellipsometers existing on the market

- The Auto SE provides a unique confocal Vision System providing two main advantages:

- Exact positioning of the measurement spot on a sample

- Selection and measurement of only the front reflection for transparent substrates

- The Auto SE is a highly featured instrument including: XYZ motorized stage, integrated microspot optics, automated selection of 8 spot sizes, and the unique MyAutoView vision system.

- The Auto SE is controlled by the Integrated Auto Soft software platform, providing:

- Ease-of-use with a new GUI generation based on the use of icons and internet like hyperlink navigation

- Multilanguage capabilities

- 3 user modes: operator, engineer, service

- The Auto SE includes built-in diagnostic indicators for the automatic detection and diagnosis of problems.

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Keithley Instruments, Inc.
The Model 2636 Dual-Channel SourceMeter Instrument

The Model 2636 Dual-Channel SourceMeter Instrument combines a precision power supply, true current source, DMM, arbitrary waveform generator, V or I pulse generator with measurement, electronic load, and trigger controller all in one instrument. It represents a new, unique way of doing parametric analysis at resolutions as fine as 1fA (10-15 A), which is often required for many semiconductor, optoelectronic, and nanotechnology devices. An instrument-based, multi-channel architecture results in a 50 percent lower cost and test speeds up to four times faster than typical mainframe-based source-measure solutions. With Test Script Processor (TSP) and TSP-Link intercommunications bus, the Model 2636 lets engineers create fast test systems that are ideal for research, characterization, wafer sort, reliability, production monitoring, and a multitude of other test applications.

The Model 2636 provides cost-effective DC and pulse testing from femtoamps and microvolts up to 200V/1.5A. It also includes a PC-like microprocessor to enable easy programming and independent execution of test programs (scripts) ranging from the simple to complex, including sourcing, measuring, test sequence flow control, and decisions with conditional program branching. Because it can be easily integrated with other instruments in automated systems, it is very useful to component manufacturers and semiconductor fabricators for wafer level testing and packaged device testing.

The Model 2636 enables users to significantly reduce their cost of test for low and medium pin count devices or multiple devices and material samples. They operate as five precision instruments in a single box: SMU (source-measure unit), DMM (digital multimeter), bias source, low frequency pulse generator, and arbitrary waveform generator. These functions are controlled by TSP, which lets engineers download fully programmable sequences to the instrument to be executed within the instrument. This eliminates communications and PC overhead, significantly improving throughput gains while allowing complete flexibility in controlling and adapting to different test situations.

A TSP-based system is capable of storing and running thousands of lines of code for predefined device tests that include limit comparisons, pass/fail decisions, parts binning, and others. They all work with or without a PC controller during test execution. Digital I/O can directly control probers, handlers, and other instruments, while TSP-Link allows users to execute high-speed automated tests across multiple channels and instruments without GPIB traffic. This results in test time reductions as large as 10X compared to older sequencing instruments, with 2X to 4X test time reductions common in component testing.

In addition to TSP, Keithley's TSP-Link master/slave connection provides a high-speed, low-latency interface to other TSP-based instruments, enabling simple multi-box and multi-instrument software control. A major benefit is easy scalability of Series 2600 test systems according to present and future needs. Multiple dual-channel (Model 2636) units can be integrated seamlessly without a host mainframe. This mainframeless scalability allows system sizes up to 32 channels per GPIB address, while minimizing cost, rack space, and time required when adding future channels.

Developing multi-instrument characterization or ATE systems for basic R&D and high-speed production testing has been a major challenge in the past. Keithley addresses this problem with two free software tools that greatly simplify systemization of the Series 2600 SourceMeter Instruments. For R&D and curve tracing applications, Keithley's LabTracer(™) 2.0 software controls up to eight SourceMeter Instrument channels to perform device characterization with no programming whatsoever. This software allows the user to fully configure each channel, run device parameter tests, and plot test data - simply and easily.

For high-speed production applications, the Test Script Processor is programmed with an uncomplicated BASIC-style programming language that runs in real time on the instrument. The intuitive, easy-to-use interface is compatible with all the popular programming languages.

Keithley provides built-in test scripts for sweeping, pulsing, waveform generation, and common component tests. A number of test scripts are included in the instrument, while others can be downloaded at no charge from the company's Web site. These pre-written factory test scripts can be used as supplied or easily customized, allowing production users to get their systems up and running faster than ever.

Users can develop custom test scripts in other ways, including a free programming tool called Test Script Builder that helps users create, modify, debug, and store TSP scripts using its simple command language.

The user's scripts can be downloaded from the PC to the master SourceMeter Instrument and saved in its non-volatile memory. Sixteen megabytes of total storage allows up to 50,000 lines of TSP code and more than 100,000 readings. Studies have shown that by using TSP and its associated software, users can cut system development time by 50 to 75 percent compared to previous generations of test sequencing instruments.

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Tres-Ark, Inc.
AutoLytics, an automated CMP monitoring system

The FractalFill product line was designed in response to customer requests for a chemical management system that would provide precisely blended chemical mixes, in an always-ready state, with interactive control features. The technology incorporates three core areas of expertise:

Analysis - detects and precisely measures the chemical mix Control - ensures accurate chemical composition Delivery - always ready precision blends Patented FractalFill blending products have the following notable features sets: concentration and volume control with analytical and control hardware chemical mix is in an always ready and supplied mode real-time control and dispense of dilute chemical mixes patented auto-replenish chemical blending "Point-of-Use" chemical management feed-forward/feed-back control of the chemical management process remote operation capabilities modular design Four standard models are available to meet the needs of specific facilities: TAKLDM - Single chemical mix, single tool TAKLDM+ - Single chemical mix, multiple tools TAK M2, 3, & 4 - Multiple chemical mixes, single tool TAK M2, 3, & 4+ - Multiple chemical mixes, multiple tools

The significance with the FractalFill controller is that the wet bench is always in a chemistry ready and supplied mode, with an analytically confirmed blend. The control electronics provide extreme mean time before failure, and the layout provides "at-a-glance" troubleshooting with visual indicators for all inputs and outputs. The technician can control, change and alter the machine's operations remotely.

The open architecture of FractalFill products can be stacked into a tower for the smallest footprint, or used as a modular package capable of being integrated into a wafer manufacturing tool. Multiple ports are available for tool interface and factory host automation allowing it to be connected into any system.

FractalFill Blending Products were introduced to the market and qualified to process in 2007 at three unique install locations.

One of the crucial elements in this process which requires tighter controls is the chemical area. If the chemical is outside of the mix ratio, the wafer can be improperly processed and, as a result, scrapped.

If chemicals are not ready to go when needed, process down time can cost up to $1M per minute. Engineers and fab managers are requiring that chemical preparation steps must include chemical management systems with interactive levels of control to ensure that the chemical mix is 100% accurate the first time, and that the mix is always ready for the manufacturing process.

FractalFill characteristics combine to form a proven industry first technology which provides copious advantages to the customer:

• increased wafer throughput/yield - no wait time for chemical delivery
• minimized ambiguity in chemistry applications increased productivity
• quick return on investment (1.5 months)
• tool to tool variability minimized
• reduces chemical consumption and waste, and extends bath life

Noted in some of the above advantages, FractalFill Blending Products are environmentally friendly products. They greatly reduce chemical consumption and waste, and thus far there has been zero chemical waste in all products in production. The controller blends the chemicals using an algorithm that measures the chemical concentration compared to the tank level. The tank will contain homogeneous solution before the tank is full. Any chemical that goes unused at the process line is recirculated and blended back to target concentration. The reporting tools also provide the tool owner data on the quantity of chemical used in previous recipes. This allows chemical inventory logistics to become more fine tuned and accurate.

The FractalFill product line has been recognized by customers and industry experts as the technology to fulfill the current and future semiconductor manufacturing requirements. Paul Mertens PhD, Program Manager Ultra Clean Processing, from IMEC stated:

Future developments will change the way we look at chemistry blending, blending limits will be much narrower and variations on the blend are not accepted. The FractalFill™ solution has an outstanding accuracy and repeatability of blending chemistries as a result of the design of the solution. We believe it's a good technology and the market potential for this type of technology is increasing.

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Advanced Energy Industries
Paramount RF-power delivery system

A key aspect of the this platform is power-delivery accuracy and control for increasingly complex film stacks and fine features sizes. The 3kW Paramount system is well suited for both etch and deposition processes in semiconductor, FPD, MEMS and solar photovoltaic manufacturing.

Next-generation device fabrication processes feature anti-reflective coatings, hard masks, cap layers and stop layers in their recipes. Process designers must account for these layers while at the same time accurately etch or deposit the primary layer that may comprise multiple compositions and doping profiles.

The Paramount platform has been engineered to accommodates these complexities with ultra-accurate power control and delivery across the full output range both on and off 50 ohm for seamless process transitions in etch, strip, PECVD, HDP-CVD, PVD and PEALD. Where pulsing is required to enable next generation process steps, the Paramount system’s optional pulse and pulse synchronization features offer the widest pulse frequency range available, according to the company. The system is able to keep pace in real time with the most abrupt plasma impedance changes, and therefore enables faster transitions, shorter process steps and reduced process times. Optional frequency tuning is performed virtually instantaneously (within msec).

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Carl Zeiss NTS GmbH
LIBRA 200 MC

Libra 200: Field Emission Gun (FEG) Energy Filtered

Transmission Electron Microscope (EFTEM). Electrons generated in the FEG are accelerated to 200 kV and interact with the sample atoms in several ways while crossing it. After the sample the transmitted electrons are analysed.

The EFTEM allows imaging down to the Angstrom scale and spatially resolved chemical and crystallographic analysis, so it is necessary in all important sectors of semiconductor industry:

• R and D: characterization of new materials (high k, low k) and imaging of the most advanced devices
• Engineering: device shape and dimensions optimization (gate oxides, gate shape, spacers, via etch).
• Production and reliability: Physical failure analysis (root cause determination by imaging and chemical analysis), electromigration in back end metal lines.

The above mentioned EFTEM applications often require the analysis of the spectrum of the energy lost by the electrons while passing trough the sample. The measurement accuracy is affected by the energy spread of the primary beam electrons, which is about 0.7 eV.

The monochromator (MC) reduces this spread by a factor of 7 to values around 0.1 eV. Therefore the capabilities of the instruments are greatly improved as outlined below.

Improved energy resolution allows to determine the band gap variations throughout a layer. Very important in porous materials like low k materials or materials with a composition gradient like some of the gate oxides.

- Improved energy resolution enables chemical and structural composition, by giving access to details of the near edge structure.

This is important for interfacial layers, like gate oxide interfaces, which critically influence the electrical properties of the device.

-Reduced energy spread contributes to extend the information limit.

Hence it improves the capability of the instrument to deliver highly spatially resolved images.

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INFICON
Sion plasma arc detector

The Sion plasma arc detector provides real-time, high-power analyses of plasma micro-arcing, which can cause damage to the target, the film being deposited, and the wafer surface in chemical vapour deposition and etch processes. Sion employs the FabGuard integration and analysis system to detect arcs that were previously undetectable. Sion’s performance does not affect the tool’s RF delivery system characteristics. The non-intrusive clamp-on design provides a compact sensor that connect directly to the process chamber’s high-power RF delivery system to collect voltage and current information at speeds up to 20kHz.

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Pfeiffer Vacuum
CMR/CCR PicoCube multi-axis scanning stage

The CMR/CCR ActiveLine vacuum gauges feature a ceramic technology sensor that reportedly prevents memory effect, provides greater resistance to corrosive gases, good temperature compensation, and better wear properties. These transmitters operate independently of the type of gas that is being employed. The output signal, which ranges from 0 to 10V, features an integral error signal. The robust ceramic diaphragm design is less sensitive to process-induced effects and can withstand millions of atmosphere cycles and bursts. Signal processing produces and optimizes measurement limit down to the smallest possible measured value of 10-5 mbar with high stability of the measured values.

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RASIRC
Steamer UHP 125

RASIRC next generation high-purity steam generation system called the ‘Steamer UHP 125’. With a reduced footprint, it can directly replace torches, bubblers, and direct water injection systems in 6’’ ,8’’ , and 12’’ furnaces as well as in other applications where flow rates of up to 12.5 slm of pure water vapour are needed. It has the ability to control flow into vacuum or atmospheric pressure systems. It generates Ultra High Purity steam from de-ionized water without hydrogen or oxygen.

Steamer UHP 125 is a safe, non-combustible system, as it does not require hydrogen and oxygen to generate water vapour. Water contaminants, including dissolved gases, metallic impurities, and particles are removed, resulting in purity equal to or better than pyrolytic steam created by burning oxygen and hydrogen.

The Steamer uses de-ionized water, which is inexpensive and widely available. A highly flexible system, it automatically controls delivery pressure, temperature, and the directly related mass flow rate so it can be adapted for many applications. It can be operated locally or remotely with an optional 0-5V ‘DeviceNet’, or ‘Modbus’.

Water vapour is used with rapid thermal processing (RTP), atomic layer deposition (ALD), plasma stripping, immersion lithography, diffusion, wafer cleaning, and to control humidity in cleanrooms.

This next generation design has a footprint of 12” length by 6” width for a steamer that is 65 percent smaller than RASIRC’s full-size steamer. At only 12” high the steamer is now small enough to fit on 6” diffusion furnace shelves and the purifier is integrated within the cabinet rather than being externally mounted. Volume is now 0.5 cu.ft. - a reduction of 75 percent.

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Digitron Engineering Services GmbH

Share an outsourced Service & Support Engineer for the Photovoltaic and Semiconductor industry.

Digitron Engineering Services GmbH, are based in Munich, Germany, offers innovative and unique cost reducing outsourcing services exclusively to semiconductor and photovoltaic equipment manufacturer and tool suppliers, world-wide. We pride ourselves in having secured partnerships with the world leading suppliers of hi-tech-tools and machinery for front and backend manufacturing equipment. We are an independent service and support organization, offering technical support from our bases in Munich (HQ), Dresden, Germany, Moscow (Zelenograd), Singapore and in the US, California and Massachusetts.

For each client, we act as service & support outsourcing partner and supplement their service and support departments, or act as their authorized service partner.

Digitron has extended its international service bases to provide their clients with even more service outsourcing opportunities. Particularly at such industrial locations were the costs of a fully owned and operated manufacturer service organization are often prohibitive.

Additional our existing outsourcing services activities, we recently developed a very interesting new outsourcing model for the Semi and PV market. In 2008, we launched a new outsourcing service product, the so called "Share an Engineer" concept. The idea is simple - one can share a qualified Digitron semiconductor or photovoltaic support engineer with other Digitron systems and tools manufacturers clients, and minimize their own outlay and cost. This new outsourcing product allows companies to provide fast, efficient, world-wide technical service and support their customers on site - under their control, by not establishing their own subsidiary remotely. This helps them to save financial and human resources and manage their own internal technical staff more efficiently.

For equipment and tool suppliers in the Semi and PV industry it is necessary to supply on-site technical support. Based on the number of installations and distance it would seriously minimize their profit or even exceed their operative budget having their own local Service Representative and infrastructure on-site.

By using Digitrons "Share an Engineer" concept they gain the following advantages:

• be more competitive due to local presence
• substantial savings compared to own solution
• share engineers and costs with other Digitron clients.
• facilities and infrastructure already in place
• prioritized spare part handling and local storage
• free telephone Support for their customers
• guaranteed reaction time
• native German or local Engineer
• engineer lives at location
• pay only for the support clients really need or consume
• predictable, budgetary support cost up front and most important -Digitrons Engineers appear as working for Clients company

In March 2008 a German customer of Plasma and Ion Beam Technology has placed the first "Share an Engineer" order to support their new installations in North America. They plan even to use the same model for upcoming installations in Far East.

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MASER Engineering
Advanced F/A services for the 90nm copper technology and below

MASER Engineering has extended her test and diagnostic services with advanced tools for Failure Analysis of integrated circuits based on copper CMP technology and with device geometries of 90nm and below.

This technology is not only available for frontrunner Integrated Device Manufacturers (IDM) but are more and more used by Fabless Semiconductor manufacturers in their advanced chipsets. The availability of the 90nm process node through major wafer foundries helps the Fabless to close the technology gap. These companies are often fully focused on their core activity: advanced chipsets and system design support tools. Their main product flow is handled by wafer foundries and assembly/test service companies. What rests is a need for an independent qualification and F/A service supplier that can meet up with the requirement dictated by the technology run. MASER Engineering have recently expanded the F/A capabilities with a set of over 15 advanced tools for the current and next generations F/A requirements by the IC technology developments. These facilities are available including a knowledgeable staff of engineers.

The expansion of the MASER Engineering F/A services addresses four main issues with the new technology nodes: decreasing feature size, new materials for conductors and isolators, more functions on a chip and the more complex packaging.

The new facilities start with new 2D and 3D X-ray and scanning acoustic microscopy with submicron resolutions. Another set of tools improves the sample preparation techniques. Laser-assisted plastic removal, dual Argon beam milling and polishing, single chip Chemical Mechanical Polishing tools and rewiring by semi-automatic wire-bonders are used to prepare stacked die packages and system-in-a-package modules. Also backside analyses of multilevel metal chips use these tools in order to get access to the active area for fault localization techniques. The next expansion is dedicated to first silicon circuit edit requests. In the prototype phase, IC designers have suggestions to change interconnect of non-functioning first silicon chips. MASER Engineering acquired the first European OptiFIB-IV system of DCG systems. This system has a coaxial NIR optical and Ga+ Ion column that allows both front- and backside circuit modifications. Further F/A equipment expansion is in Scanning Electron Microscopy, both Tungsten and Field Emission Gun types, a Dual FIB/FEGSEM beam system for slice and view operations, TEM sample preparation and precise fault location imaging. To meet the highest resolution in electron microscopy, MASER Engineering added a FEI 200kV TECNAI Field Emission Gun X-TWIN Scanning Transmission Microscope to the available F/A equipment list. All equipment is placed in the almost doubled laboratory area of MASER Engineering in Enschede, The Netherlands.

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T5

T5’s technology platform designation is Remote Integrated Management System (RIMS) and is firstly being developed to manage Thermal ancillary services provided by TCU’s / Chillers. Thus the first product variant will be TRIMS (Thermo RIMS) which will provide remote management and remote diagnostic evaluation of TCUs. TRIMS will be deployed using its own network - offering intelligent communications capabilities which will permit the online management and control of Chillers. In contrast with existing fault detection systems, T5’s technology identifies fault patterns before the actual fault occurs. Thus, T5’s technology provides for predictive maintenance of Chillers and eliminates the need for unscheduled downtime associated with the occurrence of a fault. The predictive maintenance associated with T5’s solution will significantly reduce the service and support costs - while the elimination of unplanned downtime could save an average-sized wafer fabrication factory between €2 million and €5 million a year.

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Advanced Micro-Fabrication Equipment Inc. (AMEC)

It took just 3 years for the newest Asia-based global semiconductor equipment provider to spring forward with a suite of high-productivity Dielectric Etch and High-Pressure Thermal CVD tools-leading-edge process equipment with very competitive performance for processing 65-to-45-nm devices and extendable to 32-nm device processing. These tools also promise to transform the economics of making semiconductors. Founded in August 2004, Advanced Micro-Fabrication Equipment Inc (AMEC) leveraged SEMICON Japan 2007 to unveil its new Primo tool family and reiterate its mission: to provide leading-edge tools for critical process steps that offer higher productivity and superior on-wafer performance at a lower cost of ownership. But this is no ordinary start-up. In its short life, AMEC has raised more than $100M from elite global VCs, financial institutions and corporate venture funds that include Goldman Sachs, Walden Intl., Lightspeed, Qualcomm, Samsung Ventures and others. The company is also nearing closure on an additional funding round. This, in an industry where the barriers to entry are extraordinarily high and funding is thin. The executive team boasts a who's who of the global semiconductor equipment industry. In fact, its top executives and technologists are inventors of more than 200 patents. The Board of Directors and Board of Advisors contain a selection of the world's most highly respected business and IC technology executives who were drawn to this start-up for its differentiated technology and strong customer value proposition.

With its R&D and manufacturing hub in Shanghai, AMEC has also built an extensive infrastructure of regional offices in Japan, Korea, Taiwan and Singapore to enable the sale and support of its advanced technology solutions globally. In numerous wafer demos, AMEC's Primo D-RIE and Primo HPCVD tools demonstrated better on-wafer performance than the competition. Three beta tools have already been installed at leading-edge fabs in two Asia regions. More systems are slated for shipment this year to multiple regions in Asia. Exhaustive process and hardware marathon wafer runs at AMEC's R&D facility consistently demonstrate productivity improvements of more than 35% and a CoO gain of 35% when compared to competitive tools. Interest in AMEC is high.

Beyond the differentiated, cost-efficient Etch and CVD tools, the company's Asia-based business model is viewed as a distinct advantage.

Not only does it afford regional proximity to leading fabs, it also offers unique cultural advantages. With more than 75% of the world's ICs now produced in Asia, the time is ripe for a strong new supplier of advanced process technology with executive leadership and R&D firmly planted in Asia.

AMEC is in the right place at the right time: 75% of ICs are produced in Asia; time has arrived for a credible new Asia-based innovator to provide higher-performing technology at the leading edge with lower CoO advantages.

Corporate progress: Substantial funding, promising process brain-trust, high-profile global advisors, well-established global sales & support infrastructure.

Substantial technology gains: Developed and commercialized cutting-edge (65/45-nm) tools with extendibility to 32nm devices. Tools demonstrating 35% productivity and CoO gains when compared to nearest competitors.

Significant customer traction: 3 beta tools already in the field; more slated for shipment this year.

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Nanoplas

Nanoplas is a French start-up company that has developed a new process called HDRF®, providing the ultimate in dry cleaning for advanced 3D silicon integration technologies.

HDRF - High Density Radical Flux - technology is based upon a proprietary ICP plasma source that makes it possible to produce 50 to 100 times more active species than competitive systems and eliminate plasma-induced damages. For the first time in plasma processing, samples are not exposed to electrical charges; substrates are processed in a “soft” high density flux of neutrals that is ideally suited for the new generation of embedded technologies.

Nanoplas’s current target application is advanced flip chip activation and isotropic etching for MEMS dry release, but the variety of available chemistries and process settings offers flexibility for many new applications. Additional competitive advantages include a high throughput, small footprint, and low COO at a low initial cost. Nanoplas is already enjoying rapid market acceptance, with orders received from large players in the UK, US, and Japan. The company expects to ship 10 to 15 systems this year and to reach over $10 Million in sales within 3 years.

In the ever-shrinking world of nanoelectronics, Nanoplas’s ground-breaking dry process technology provides the damage-free precision control that will be crucial to the development and mass production of the next generation of nanodevices.

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RFIC Solutions

RFIC Solutions Inc, is a fabless semiconductor company focused exclusively on wireless Solutions, with headquarters in San Jose, CA . RFIC Solutions designs highly integrated system on chip (SOC) and system on a package (SOP); custom ICs, MIC and offers optimized solutions for any wireless systems including cellular, Wi-Fi, WLAN, WiMax and ultra wideband systems.

RFIC Solutions design IP cores are developed using state-of-art GaAs, InGaP/GaAs, InP, Si and SiGe Semiconductor processes utilizing MESFET, pHEMT and HBT devices. RFIC Solutions works closely with its customers throughout the design process in refining and developing MMICs for high frequency and broadband communication markets. They have expertise in LNA, PA, Switch and complete transceivers for any wireless system including WLAN, WiMax, PCS and Cellular applications.

RFIC Solutions Inc offer Design Services in MMIC, RFIC, RF Modules and RF systems. They have done 60 different designs covering DC to 40 GHz on various process like GaAS pHEMT,GaAS HBT,Silicon CMOS,SiGe BiCMOS & GaAS MESFET provided by foundry partners like Triquent, Jazz, GCS, Tower & TSMC.

The RFIC Solutions Inc goal is to provide innovative design services for complex RFIC requirements, at highly competitive rates, in the rapidly expanding communication and consumer wireless markets.

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T5

T5’s technology platform designation is Remote Integrated Management System (RIMS) and is firstly being developed to manage Thermal ancillary services provided by TCU’s / Chillers. Thus the first product variant will be TRIMS (Thermo RIMS) which will provide remote management and remote diagnostic evaluation of TCUs. TRIMS will be deployed using its own network - offering intelligent communications capabilities which will permit the online management and control of Chillers. In contrast with existing fault detection systems, T5’s technology identifies fault patterns before the actual fault occurs. Thus, T5’s technology provides for predictive maintenance of Chillers and eliminates the need for unscheduled downtime associated with the occurrence of a fault. The predictive maintenance associated with T5’s solution will significantly reduce the service and support costs - while the elimination of unplanned downtime could save an average-sized wafer fabrication factory between €2 million and €5 million a year.

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Alcatel Micro Machining Systems
AMS 3200/AMS 4200 cluster tools

The Alcatel AMS 3200/AMS 4200 cluster tools provide recent process capabilities in DRIE for etching silicon materials and glass-like materials, as well as PECVD solutions for SiO2 and Si3N4 isolation layers. Wafer handling modules are based on BROOKS field-proven stations. Process modules are equipped with a high density, low-pressure ICP plasma source for Bosch DRIE silicon etching and etching of deep SiO2, quartz, fused silica, borosilicate, and blass, and PECVD deposition of SiO2 and Si3N4 at room temperature. These cluster tools are dedicated to volume production of MEMS and 3D semiconductors.

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Obducat
Sindre Manufacturing system for NIL

Company Background Obducat is the world-leading supplier of lithography solutions for production, replication of advanced micro- and nanostructures for industrial mass production and for R&D. Obducat also offers scanning electron microscopes for metrology purposes. Leading consumer electronics manufacturers as well as ivy league universities around makes use of the unique benefits embedded in Obducat's key technologies. The company was founded in 1989 and with its more than 15 years experience of purpose build lithography solutions, Obducat is recognised as the most experienced player within the high resolution lithography industry. Obducat is today the market leader with the largest installed base worldwide of NIL systems, consisting of about 80 systems. The technologies are covered by a strong patent portfolio of some 100 approved patents. Obducat has a well-established supply-chain with a large number of agents, distributors and partners, such as Canon Marketing Japan.

Application areas Obducat provides key lithography solutions for several different application areas in which the customers are provided with our viable and cost-effective lithography solutions that will give them a competitive edge in delivering break-through applications and enables them to achieve improved profitability and success. Obducat’s NIL-technology has been deployed in mass production since 2006 within the LED industry. The current development in the Hard Disk Drive (HDD) industry focused on patterned media constitutes a significant opportunity for lithography suppliers. Obducat is able to offer a turnkey lithography solution, ranging from the high accuracy mastering technology, stamp replication and finally high throughput (600 dph) imprinting capability. Obducat is also active in other application areas such as Flat Panel Displays and semiconductors. This requires uniform and high precision imprint technologies over large areas as well as accurate layer-to-layer alignment accuracy, alternatively utilizing the NIL technology to imprint several layers in one step. Products and Services: Obducat’s product portfolio encompasses: -         Equipment -         Stampers -         JDP (Joint Development Project) -         Licenses NIL (Nano Imprint Lithography) The Nano Imprint Lithography (NIL) equipment product range consists of two product lines, the Sindre®-model for mass-production and the Eitre® model for R&D. All NIL systems are based on the well known SoftPress®  technology, which allows pressure to be applied to the stamp and substrate hydraulically without using any rigid pistons. This ensures complete parallelism between the stamp and substrate over large areas, thus resulting in a uniform replication to the substrate. IPS® / STU® Process Obducat’s High Volume Manufacturing (HVM) solution incorporated in the Sindre® systems is based on a two step process: The first step replicates the master stamper into an IPS® (Intermediate Polymer Stamp). This process eliminates contact between the master stamp and the hard substrate, resulting in increased master stamp lifetime, minimized void areas and increased contamination control. The second step replicates the UV transparent IPS®  to the final substrate, utilizing the proprietary technology called STU®   (Simultaneous UV and Thermal) imprint allowing to perform imprint at constant temperature. EBR (Electron Beam Recording) By combining Obducat CamScan’s 35 years E-beam experience with Obducat’s extensive knowledge of mastering process, we can provide e-beam based lithography mastering dedicated to produce todays and next generations of storage media applications. Stamp Manufacturing Obducat delivers high quality stampers used in the imprint replication process with features ranging from sub 30 nm up to the micrometer scale. In order to assure contamination free stampers, the production is carried out in a Class 10 clean-room environment. Available stamp materials are Si, Ni, quartz and polymer. Complete solutions Obducat’s customers have the advantages of utilizing the complete product and technology portfolio within Nano Imprint Lithography and EBR mastering services, including the required machines, processes and development resources. This service allows customers to quicker bridge the gap between the development phase and the integration of machines and tools directly into the customer's production line. Back to top

SiTime
World's Thinnest Programmable Clock Oscillators

Digitization, miniaturization and improved aesthetics are worldwide trends in electronics, as evidenced by the massive commercial success of ultra-thin mobile phones (Motorola’s RAZR, Samsung’s Ultra II family) ultra-compact MP3 players such as the iPOD, and increasingly smaller, thinner digital cameras from Japanese leaders such as Sony, Canon and Nikon. The worldwide trend is towards thin and light electronics equipment, because it is smaller, convenient, and fashionable.

An electrical clock signal is the heartbeat of any digital electronics system. Traditional clock sources, such as quartz-based oscillators, have been the clock sources in electronics for decades. However, crystal-based clock oscillators are rarely thinner than 0.8mm due to constraints in their physical properties - the material is brittle and is subject to cracking, warping, and electrical instability. Quartz-based clock oscillators are frequently the key components that prevent thinner electronics equipment. In addition, they generally have large footprints and have long lead times for availability, especially for custom frequencies.

SiTime has revolutionized the miniaturization of clock oscillators. SiTime’s MEMS-based clock oscillator (SiT8002XT) is available in tiny footprints, significantly smaller than any quartz-based clock oscillator, but even more importantly, in a package that is only 0.27mm thick. Such an extra-thin package, which is a three-fold improvement over the best quartz-oscillator packages, can enable a new generation of miniaturization and improved aesthetics for a variety of applications, such as extremely thin digital cameras and mobile phones. The SiT8002XT can also be used in next-generation Smart Cards and SIM cards, potentially accelerating the convergence of electronic wallets and cell phones and opening up new revenue streams for mobile carriers.

SiTime’s SiT8002XT also offers other benefits - the devices can support any custom frequency between 1 MHz and 125 MHz with deliveries in a matter of days rather than weeks or months, which is of massive value to digital designers and supply chain specialists worldwide. Mechanical robustness is inherent in all SiTime products - they can withstand shock up to 30,000 Gs, as well as vibration resistance up to 40 Gs, providing outstanding performance for demanding automotive and consumer electronics applications. Finally, the devices are environmentally friendly - they are available in RoHS compliant lead-free packaging.

SiTime’s SiT8002XT programmable oscillator provides inherent benefits of being the world’s thinnest clock source (by a factor of three) with the outstanding shock and vibration resistance. These devices will usher in a new era of environmentally-friendly, thin, light, fashionable equipment and potentially develop new business models for mobile carriers and electronics manufacturers.

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Micralyne

http://www.micralyne.com/index.html

Based in Edmonton, Alberta, Canada, Micralyne Inc. has evolved into one of the leading MEMS manufacturing companies in the world. Micralyne leads the industry by focusing on sustainable profit and customer fulfillment. Micralyne's core business is to develop and manufacture MEMS (Micro-Electro-Mechanical-Systems)-based products. Micralyne's products are found in telecommunications networks, automobiles, medical devices, and chemical analysis instrumentation.

Micralyne added 11,000 sq. ft. of new plant space and 4,500 sq. ft. of new office space built during 2007 and now has over 55,000 sq. ft. in operation. This included an increase of clean fab space by 83% and clean test & assembly space by 128%.

Please give three reasons why this nomination should win an award:

MARKET EVALUATION Micralyne is Canada's only independent MEMS manufacturer and has become known as one of the world's leading independent OEM MEMS manufacturers. Transitioning from a university-owned not-for-profit to a privately held corporation, Micralyne Inc. has generated long term growth averaging 20% annually, growing from $1.7 million in 1994 to over $23 million last year. During this time the company has been profitable every year except one, a result unequalled by any other company in the MEMS industry.

TECHNOLOGY INNOVATION

Technology Innovation is a key component to Micralyne's success. Since becoming an independent manufacturer ten years ago, Micralyne has followed three key principles:

• Long term-sustainable profitability
• Customer focus
• Growth

These three principles have helped drive its innovation and manage its success. By understanding its customers and the market contexts in which they operate, Micralyne is able to add value to each customer's organization. This allows Micralyne to creatively address its client's needs and anticipate future involvement in delivering innovative technologies to move its client's ideas forward into reality.

INFLUENCING THE SMALL TECH INDUSTRY

Micralyne recently celebrated its tenth year since becoming Canada's first and only independent MEMS foundry. Over the ten years, Micralyne has succeeded by adding value to its customers and by increasing revenues continuously. In addition to this growth, staff levels and facility space have increased over the past year. Micralyne's past and current success is evidence that with a strong business plan, an independent foundry can not only be profitable but can be a benchmark for the MEMS industry.

IMPACT ON SOCIETY

MEMS technology is driving significant innovations in many parts of the economy, including communications, life sciences, energy and transportation. Micralyne Inc.'s top executives actively lead a highly focused engineering and manufacturing team that has developed some radically innovative applications for Micralyne's international customer base:

• Optical switch components installed into telecommunication networks to facilitate the increase in internet bandwidth to homes and businesses.
• Microfluidic devices that lie at the heart of bioanalysis instruments and that are used to detect the presence of diseases like HIV and cystic fibrosis or analyze DNA from a blood sample.
• These miniature devices are able to reduce the turnaround time for analysis results from days to minutes.
• A component within printing equipment typically used to print most of the widely read, high gloss magazines in the world today.
• Implantable drug delivery devices
• These devices can be implanted into a human body and used to deliver particular drugs when activated by an outside source, such as a remote control.
• This new technology is an important step for the effective implementation of therapeutic regimens. It also highlights the huge potential of using MEMS devices in the life sciences industry.

CONCLUSION Micralyne has proven that it is a leader in its industry with a successful business model that includes long term-sustainable profitability, customer focus and growth. It has been a long climb from 1988 when Micralyne was a university-owned not-for-profit organization to today's highly competitive, highly profitable independent organization. Micralyne looks forward to continuing its success by bringing innovative MEMS designs and processes to market, and by continuing to add extraordinary value to its customers.

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Silex Microsystems

Silex manufactures Micro Electro Mechanical Systems (MEMS) - each one tailored for specific customers and applications. We are a leading dedicated MEMS foundry that brings MEMS technology and capacity to device makers and other high-tech industries all over the world. Our customers are found in the medical, biotech, telecommunications and consumer electronics industries. We also produce MEMS for the automotive and other manufacturing industries.

Mastering process and production technology
Silex strives to be one of the most advanced and efficient foundries in the MEMS industry working together with customers to give them the benefits and advantages offered by MEMS technology. We have extensive knowledge of MEMS processing and production technology. And this knowledge is the key to our ability to serve customers and contribute to making their products successful.

There are considerable economies of scale in MEMS production. The marginal cost of producing one more MEMS chip in an existing factory is low. We produce MEMS chips for large volume customers and developing customers having the potential to become volume customers. This has enabled us to add manufacturing capacity based on customer needs and successes.

Customer partnership
Silex’ strategy is to develop strong and enduring customer relations and provide high level of service. Our customers’ success is our success. And customers from around the world already trust us with their manufacturing needs.

Silex has today a solid customer base with more than 70 customers, which is considered large for the industry. Today, Silex manufactures MEMS products in volumes for ten of these customers. This broad customer base gives Silex the potential for a major increase in volume production.

Products

There are three main categories of MEMS:
- Sensors
- Actuators
- Three-dimensional structures

Sensor based MEMS sense pressure, speed, direction, position, temperature and light, among other things, and are used in the automotive, life science and consumer electronics industries. MEMS microphones also belong to this group, which are becoming more and more common in mobile phones. Actuators, for example optical switches, RF switches and micro robots, work through movement. Typical applications for pure MEMS structures are microneedles and lab-on-chip products. Examples of relatively new and interesting areas of development are RF MEMS, which can send and transmit information, and fuel cells in which the MEMS chip generates its own power supply.

Today, Silex manufactures many 70 unique MEMS products – each one tailored for specific customers and applications. The company’s largest products, in terms of volume and value, are applications for handheld devices and lab-on-chips. Several of the MEMS products that Silex manufactures contain microsensors, which are used for example to measure pressure in the coronary artery. With a cross sectional area of less than 0.1mm, they are among the world’s smallest. Silex also produces microneedles that are used to inject medicines and to measure biological signals, which can be used to diagnose malignant melanoma. Silex manufactures optical switches for the telecommunications industry, where a tiny chip can accommodate movable micromirror arrays that transmit signals in a fiber optic network. For other industries Silex also manufactures, gas sensors, micromirrors for lithographic equipment and micromotors for complex instruments.

Manufacturing process
MEMS are manufactured from wafers of silicon, glass or quarts, on which patterns and surfaces are etched and deposited. In this way, sensors, mirrors and a number of other three-dimensional structures are successively formed. Different parts can be made to be conducting, isolating or reflecting. The structures that make up the chip are very small, often smaller than dust particles. Production therefore takes place in clean rooms where the particulate in the air is controlled and kept below defined levels. Different limits apply in different production areas. A corridor links the different production areas together. Air supply in a clean room is unidirectional, filtered through roof mounted diffusers and extracted from the lower part of the room. Clean rooms are entered via an airlock where people change into special sterile clothes. The clean room’s unidirectional air flow and overpressure provide protection against contamination from adjacent areas.

Depending on level of complexity, MEMS products are made of 1 to 20 mask layers on wafers. The mask layers are created and removed in different steps of the process, comprising depositing, lithography, etching and bonding. Each wafer can accommodate from one all the way to 100 000 MEMS chips. After wafer treatment has been completed, it is cut into chips using a diamond saw. Wafers with a diameter of 6 inches are often used in the MEMS industry. But other wafer sizes are also used. Manufacturing costs are lowered using larger wafer sizes, since the larger surface, all other things being equal, accommodates more MEMS chips. Production is done in batches of varying sizes. The wafers are contained in a cassette that accommodates up to 25 wafers that are fed to different machines. At any given time, Silex works with more than 30 different MEMS products simultaneously at its manufacturing plant.

Most of the steps in the MEMS manufacturing process are the same as those in the semiconductor industry. However, the production complexity of MEMS is considerably greater since they contain three-dimensional structures. Both industries use the same manufacturing equipment, but differ partly in terms of manufacturing technique. Within the semiconductor industry the wafer is purely used as a bearer, while in the MEMS industry it is also a part of the product itself. The MEMS industry has developed bonding techniques to join several wafers to each other as well as special etching methods to create three-dimensional structures out of the wafers.

In order to protect know-how and proprietary development processes, Silex operates under a high level of confidentiality and further developed continuously. Silex applies for patent protection for some of its processes. The reason for this is to secure Silex’ right to utilize the technology. Patent protection is used to prevent others supported by a corresponding patent from prohibiting Silex from using the technology in question.

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Tronics Microsystems S.A.

www.tronics.eu

Fast growth, highly profitable MEMS contract manufacturer of the year.

While the MEMS foundry/MEMS contract manufacturing business grew by 30% in 2007, Tronics Microsystems, a France-based contract manufacturer of custom MEMS components and microsystems and a leader in the production of custom components based on SOI-MEMS technologies, posted a 56% revenue growth at 10.5M€ (15.4M$) in the same period. The company declared that 80% of its revenues where coming from series production of products for its customers, a significantly high number in this emerging industry where a large number of products are still under development. The company also announced a net profit of 1.3 M€ (1.9M$) representing 12% of its sales revenues.

In a still emerging industry, Tronics Microsystems performance were noticeable and show a clear maturation of the supply.

Important factors of the performance
Tronics Microsystems has built its success in manufacturing customer specific components for demanding high-end applications in the medical, instrumentation and aerospace domain. Recognizing the impact and problematic that packaging and testing represent in manufacturing a reliable MEMS device, Tronics Microsystems has integrated those capabilities as part of its offering early in its history. 2 years ago the company increased its capabilities in this area by building an internal assembly and packaging line and increasing its characterization and test capabilities. Thanks to the high value-add of its offering its customers can rely on Tronics expertise to integrate MEMS-based solutions in their products.

This value-add differenciates Tronics from traditional foundries that focus on MEMS processing and allow them to better understand and optimize the components they develop for their customers, ensure their successful productization and manfacturing while guaranteeing the high yield and functionality of its deliveries. Tronics provides the customer solutions in building reliable supply chain for their specialised products and delivers them qualified, packaged and tested components and microsystems. In an industry driven by cost of infrastructure and yield management, the performance of Tronics show that they both assured customer satisfaction while keeping an efficient operation.

Quote from Jean-Christophe Eloy, general manager and founder of YOLE Développement:

“Tronics’ revenue growth clearly signals that the industry is maturing and we foresee a further 30 percent CAGR for the industry in 2008 and a stronger growth after 200. But profitability of the majority of independent MEMS manufacturers and MEMS units of IC manufacturers is yet to be proven. Tronics’ consistently profitable performance underscores its leadership in manufacturing specialized high performance products with high-yield, while maintaining a lean and efficient business.”

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Nanoplas
HDRF - dry cleaning for advanced 3D silicon integration technologies

Nanoplas is a French start-up company that has developed a new process called HDRF , providing the ultimate in dry cleaning for advanced 3D silicon integration technologies.

HDRF - High Density Radical Flux - technology is based upon a proprietary ICP plasma source that makes it possible to produce 50 to 100 times more active species than competitive systems and eliminate plasma-induced damages. For the first time in plasma processing, samples are not exposed to electrical charges; substrates are processed in a “soft” high density flux of neutrals that is ideally suited for the new generation of embedded technologies.

Nanoplas’s current target application is advanced flip chip activation and isotropic etching for MEMS dry release, but the variety of available chemistries and process settings offers flexibility for many new applications. Additional competitive advantages include a high throughput, small footprint, and low COO at a low initial cost. Nanoplas is already enjoying rapid market acceptance, with orders received from large players in the UK, US, and Japan. The company expects to ship 10 to 15 systems this year and to reach over $10 Million in sales within 3 years.

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Replisaurus
ElectroChemical Pattern Replication ECPR

Replisaurus’ advanced metallization technology targets micro and nanoscale metal structures used for applications within microelectronics, optoelectronics, sensors, flat panel displays and advanced circuit boards. Replisaurus’ ECPR technology redefines the fundamentals of micro and nanoscale metallization and delivers a metallization process with superior performance/cost ratio.

The integrated “ElectroChemical Pattern Replication” (ECPR) process is an enabling technology targeted at key growth markets such as integrated passives, copper pillars and 3D integration (TSV). The company has demonstrated fine pitch/high resolution capability (&#8804;280nm space) and significantly improved thickness uniformity. The Replisaurus process offers a simple and cost effective integrated solution eliminating several traditional process steps thereby reducing complexity. The number of process steps in a typical metallization flow are reduced from eight (8) to three (3), resulting in shorter cycles times and a simplified production flow.

ECPR is a fab friendly, environmentally clean process which does not use any solvents, developers or strippers and has extremely fast plating rates. The ECPR technology is a “Design Enabling” technology for integrated passives enabling advanced designs, eliminating the need for prototyping and dummy plating patterns. The electrochemical replication principle of ECPR combines the precision and resolution of advanced lithography with the ease and efficiency of electrochemical deposition into one single integrated process solution.

Consequently, ECPR is a clean technology which significantly reduces costs for equipment, maintenance, personnel, clean room, and direct materials as well as provides high throughput capabilities due to its cycletime efficiency. Replisaurus Technologies offers complete production solutions including IP enabled equipment, replication templates (masters), chemicals and technology transfer.

Competitive Advantages
The principle of direct metal depositon using ECPR delivers a number of competitive advantages in performance, cost of metallization and environmentally clean technology.

Customer Value Proposition
Compared to conventional lithography-based metallization ECPR offers:

1. Improved device performance and process control

a. Improved metal thickness uniformity, without pattern dependent variations that are inherently associated with through mask plating.
b. Low resistivity metal with very high purity.
c. Minimum line width variations and well controlled conductor profiles.
d. Short process cycles with fast process performance feedback.

2. Reduced investments in equipment and clean room

a. One (1) integrated ECPR equipment replaces six (6) tools.
b. Short cycle times enable high throughput and fewer tools.
c. Reduced clean room investments. Fewer tools need less clean room area.

3. Clean technology with reduced operational costs

a. Less direct material is consumed. Photopolymers, strippers and developer chemicals are removed from the flow and the consumption of electrolyte and rinse water is reduced. This results in both lower operational costs and a more environmentally friendly solution.
b. Reduced number of tools results in fewer operators and lower maintenance costs and energy consumption.
c. A simplified process with fewer steps is less complicated to control and leads to higher yields.

Replisaurus’ ECPR technology is a clean technology solution which redefines the fundamentals of micro and nanoscale metallization and delivers a metallization process with superior performance/cost ratio.

Replisaurus’ revolutionary ECPR™ technology cracks the code on metallization for both front end and back end manufacturers. Replisaurus is one of the very few companies whose technology is a true bridge between the FEOL and BEOL manufacturing. The ECPR technology has legs and can create the metal layers both above and below the passivation layer providing for easier integration between the IDM’s and OSAT supply chain. Replisaurus has filled an important gap in the semiconductor supply chain right between the FEOL and BEOL.

Replisaurus has attracted some of the industries top talent and as a result the company is growing rapidly. Since our A Round financing in August 2006 we went from just 4 employees to 80 employees in a little more then a year and a half. Through our recent acquisition we have expanded our product portfolio to include Nano Imprint Steppers and Chip to Wafer technologies as well as the integrated ECPR™ solution.

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SILECS, INC.
New use of spin-on dielectric materials to enable new generation of CMOS sensors

Increasing the performance requirements in CMOS image sensors (CIS) for digital cameras is driving a need for improvements in both the optical portion of CIS devices and the durability of the camera module assembly.

Enabling materials innovator, Silecs, has developed two novel uses of Spin-on Dielectric (SOD) materials to accomplish both of these objectives. Each of the new approaches uses SOD in the construction of the optical stack, in contrast to the organic photo resist-like materials conventionally employed. In the first method, a vertical light guide (VLG) structure is formed in the device backend and filled with high refractive index SOD (RI=1.65 @ 633nm) to improve optical performance. The second method employs a low refractive index SOD (RI~1.28 @633nm) topcoat, which enables easier micro lens engineering and optimization, and also offers the advantage of protecting the organic micro lens with a glass-like layer.

Silecs has applied the VLG technique to successfully integrate a VLG structure in a 0.18um and below image sensor structure and compatible with both Al and Cu backend. Unlike conventional approaches, the resulting optical stack is not diffraction-limited. Excellent planarity above the optical elements was achieved, eliminating the potential need for CMP, and dark current performance was not compromised.

Silecs has likewise demonstrated the effectiveness of the second technique, using low RI SC500 as a topcoat. The glass-like behaviour of this SOD material offers the advantage of micro lens protection during sawing and improves epoxy base-like packaging compatibility. The SOD was engineered to enable excellent planarity or conformality above micro lens array with superior film quality. The use of a low refractive index topcoat enables focal lengths in the intermediate range (between backend without topcoat and backend with a common organic topcoat).

Further, the technique introduces an extra degree of freedom in the design of optical system focal length through control of the SOD bake conditions. When the focal length is kept the same for an existing integration scheme with or without topcoat, the same optical performance is obtained. This is achieved by adjustment of micro lens height for each case. Again, there is no degradation in dark current performance.

The two integration schemes (VLG and lens topcoat) are complementary, and when used in combination, will help enable a new generation of more efficient, sensitive and reliable CMOS sensors that have a smaller footprint. The work was conducted at Silecs' state-of-the-art production facility in Espoo, Finland. Here, Silecs' advanced enabling materials are developed and manufactured in semiconductor-like clean-room conditions, mirroring the production environments of the company's microelectronics manufacturing customers.

Process represents a unique new way to use spin-on dielectric materials; process resulted in significant performance improvements; process enables a new generation of more efficient, sensitive and reliable CMOS sensors with a smaller footprint. Work was conducted with leading customer in Silecs' state-of-the-art mfg facility in Espoo, Finland with production conditions that mirror microelectronics clean-room environments. Silecs is a thriving emerging player in the highly competitive electronic materials industry.

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