EuroAsia Semiconductor Home Solar IC Virtual 365 Industry Awards CleanTech 365 Recruitment 365
GMT   

Winners 2009

Materials - Enabling Award

•
Air Liquide Electronics
ToRuS: ALOHA's Total Ruthenium Solution
Air Liquide Electronics

Materials - Improvement Award

• MSG Lithoglas AG
Cool Glass - Hermetic Borosilicate Thin-Films

Metrology / Test / Yield Award

• Rudolph Technologies
Explorer Inspection Cluster

Metrology / Test / Yield Device Award

•
Agilent Technologies
B1505A High Power Test System

Wafer Processing - FEOL Award

• Nikon Corporation
NSR-S310F

Wafer Processing - BEOL Award

• Jenoptik Automatisierungstechnik GmbH
Votan G Semi System

Subsystems & Components Award

• Edwards
The Ixh vacuum pump

Subsystems & Components Enhancement Award

• Entegris, Inc
Torrento High-Flow Liquid Filters

Fab Management Award

• Maser Engineering
Outsourcing Service
   
R&D Initiative of the Year
MicroNanoSystems Innovation Award
Education Initiative of the Year
Foundry of the Year
CleanTech Award
 

Air Liquide ElectronicsAir Liquide Electronics
ToRuS: ALOHA’s Total Ruthenium Solution

ToRuS was developed in 2005 as a part of new ruthenium precursor development project in Air Liquide Corporate R&D Laboratories.

ToRuS is based on a carefully tuned proprietary formulation containing an inorganic ruthenium compound in a tailored solvent mixture. Its relatively high vapor pressure (10 Torr at 25°C) compared to other commonly available ruthenium precursors allows high deposition rates without the need for canister or line heating.


Click here to view

Several academic institutions, industrial consortia, and equipment makers in US, Asia, and Europe have evaluated ToRuS over the last 3 years. ToRuS has been successfully demonstrated to yield excellent quality ruthenium thin films by CVD and ALD with high deposition rates (1.8 Å/cycle by ALD) and good adhesion characteristics on a variety of substrates (Si, SiO2, SiN, SiC, Al2O3, Ta2O5, TaN, HfO2,and La2O3). Recently, a research team at Seoul National University has reported outstanding process performance, illustrating that highly pure ruthenium films with low resistivity (~20μΩ.cm for 20nm film), perfect step coverage in high aspect ratio features (> 95%, in AR 13), and superior thermal stability (Rapid Thermal Annealing at 750°C) can be obtained with ToRuS. Furthermore, high surface reactivity of ToRuS enables ALD at 150°C without incubation time.

ToRuS claims more than 30% reduction in material cost when compared with conventional organo-metallic ruthenium sources. In addition, high precursor efficiency in ToRuS based process results in further reduction in process cost of ownership. ToRuS is a non-flammable, non-corrosive, solution. It is an unregulated product for transportation purposes and has no obligatory labelling requirements for oral toxicity (confirmed by tests performed following the European Community, the OECD and the EPA Health Effects Tests guidelines).

Developing a cost effective Ruthenium metallization solution is a key challenge for various applications in the electronics industry. ToRuS is a proven enabler of advanced manufacturing technologies, providing elegant process solution, at the lowest cost of ownership, with proven performance. These differentiators have allowed a rapid adoption of ToRuS in production of Giant Magneto-Resistive (GMR) and Tunneling MagnetoResistive (TMR) read sensors by low temperature ruthenium ALD, and other novel applications requiring high purity ruthenium film deposition are being actively pursued by OEMs and industrial consortia worldwide. This product has promise for both the semiconductor and hard disk drive industries and has achieved recognition as an enabling material.

MSG Lithoglas AG

Borosilicate glass is well known for its chemical inert behaviour and stability. It is temperature stable and hardly dissolves in most acids, bases and solvents. It is the close-to-perfect material for semiconductor packaging in respect to its electrical, chemical and physical properties. Through being successful in special applications like anodic bonding or glass-to-metal seals, the use of glass for mainstream packaging of semiconductors was limited by lacking CMOS process compatibility and other manufacturing limitations.

MSG Lithoglas AG has developed and implemented a deposition and structuring technology, which enables the production of microstructured borosilicate glass thin-films with a thickness of 100 nm to 30 µm on a large variety of substrates at temperatures well below 100 °C.


Click here to view

The deposition of the glass is done by a plasma-assisted e-beam evaporation process. It is a high rate deposition process with at the same time low substrates temperature. With the high deposition rate typical film thicknesses of 3 – 10 µm can be achieved easily and production can be run as a cost effective batch process. Thicker layers as thick as 100 µm have been demonstrated in R&D. They have proven to exhibit low stress in the deposited layers and leverage from their thermal expansion being matched to silicon.

The glass layer can be microstructured by lift-off. Since the deposition process is working at low temperatures standard photo resists can be used for masking.

As a mainstream application the glass thin-films are used for passivation of opto-semiconductors on Si or GaAs easily meeting harsh environment reliability requirements e.g. for automotive or space applications.

The high-volume Lithoglas process is CMOS-Backend compatible and runs e.g. on SEMI standard silicon device wafer, but also allows for processing of thin-film glass for a large variety of other applications incl. Ge, InP, SiC, LiNbO3, Borofloat or Pyrex, HTCC or LTCC substrates or even flexible substrates.

The combination of a low temperature deposition process with the excellent properties of glass being hermetic, chemically stable and robust enables a unique and revolutionary solution for the passivation of semiconductors or other sensitive devices.

The Lithoglas process is a unique approach bring wafer-level-packaging to a new level of reliability. It has the potential to replace polymers in harsh environment applications and to expand the conditions of use for low cost electronics.

The cost-effective, CMOS compatible process can act as a drop-in replacement of CVD or polymer passivation leveraging from existing infrastructure ensuring excellent and stable manufacturability. The technology approach is new and inventive, matching the requirements of advanced wafer-level packaging.

Rudolph Technologies, Inc
Explorer Inspection Cluster

The Explorer Inspection Cluster claims fast, accurate and reliable macro inspection with flexible configuration of multi-surface inspection capabilities. The Explorer Architecture allows individual systems to be configured with any combination of wafer front, back, and edge module allowing the user to mix and match throughput and inspection type to best fit specific requirements and reduce cost-of-ownership.


Click here to view

The Explorer Architecture is a modular approach to wafer inspection consisting of one or more inspection modules with brightfield and darkfield illumination, a substrate handler, and software that coordinates the activities.

The Explorer Inspection Cluster is an edge and backside inspection system claiming low cost-of-ownership to the IC industry, while the NSX is used for high-volume inspection and metrology of next-generation production processes.

The Explorer’s edge and backside modules both use image-based inspection for a more in-depth data set than light scattering techniques.Controlling edge and backside defectivity has become one of the critical factors for enabling 45nm and 32nm processes, and the Explorer offers a combination of sensitivity and cost of ownership to address these issues. In addition, Discover data analysis software, offered as an option, further enhances efficiency by finding and classifying defect pattern signatures, eliminating the time-consuming task of classifying thousands of individual defects.

Agilent Technologies HSTD
B1505A High Power Test System

The Agilent B1505A Power Device Analyzer / Curve Tracer claims to be the only single box solution available today with the capability to characterise high power devices from the sub-picoamp level up to 3000 volts and 20 amps. These capability covers evaluation for new power device using wide band gap materials such as silicon carbide (SiC) or gallium nitride (GaN). The B1505A has separate modules that support high-current (HCSMU) and high-voltage (HVSMU). The B1505A also supports a high-power SMU (up to 1 A/200 V) and a multi-frequency capacitance measurement unit (up to 5 MHz). Its ten-slot modular construction lets you configure the B1505A exactly the way you want.


Click here to view

The B1505A software environment allows users to check device characteristics and detect device faults with the easy convenience of a curve tracer. Just like on a curve tracer, the B1505A supports rotary knob control of the independent sweep variable for intuitive and real-time evaluation of parameters such as breakdown voltage. The measurement setup information and data can be automatically stored to the B1505A\'s built-in hard disk drive and transferred to USB memory sticks as well as other portable storage devices. It is also easy to print graphical measurement data and to copy and paste it into reports when the analysis results are summarized.

Nikon Corporation
NSR-S310F


Click here to view

The NSR-S310F is an advanced ArF scanner for high volume manufacturing of 65 nm or smaller devices. The system uses Nikon Tandem Stage technology to increase throughput, improve alignment accuracy, and enhance long-term stability. With the throughput increased to 174 wafers per hour – a 20% increase over the previous generation Nikon scanner – cost of ownership is significantly reduced. The Tandem Stage also helps improve alignment accuracy to better than 7 nm.

The projection optics (0.92 NA) and illumination system provide superior image quality and CD control across the wafer with the low aberration and flare levels. Nikon’s fourth generation polarization control system, POLANO, and optional infrared aberration control (IAC) provide further imaging benefits.

Jenoptik Automatisierungstechnik GmbH
VOTAN G Semi


Click here to view

VOTAN G Semi, is a wafer dicing system that utilises Thermal Laser Separation (TLS). The system was developed as an alternative to established mechanical dicing saws and other laser dicing technologies to deliver a highly precise cutting edge. It is especially well suited for applications with special demands on edge quality – like optical devices or power devices with vertical current flow.

TLS-Wafer-Dicing by JENOPTIK Automatisierungstechnik GmbH is a full separation technology for semiconductor materials. The Thermal Laser Separation (TLS) process thermally induces mechanical stress in the material using a laser to perform the dicing process.

The Equipment
The JENOPTIK-VOTAN Semi 300 is a complete dicing equipment for back-end class 6 clean rooms. The JENOPTIK-VOTAN Semi 300 processes film frame mounted wafers (150 mm - 300 mm; 6“ - 12“) fully automatic. The optional handling operates one/two magazines. The JENOPTIK-VOTAN Semi 300 – including the laser – is a low maintenance equipment. The tool comes with our patent pending edge protection stretch technology and a couple of control and measurement tools (alignment camera, kerf-check microscope, code scanner).

Future options:
  • water free gas cooling
  • SECS/GEM interface
Advantages
  • Higher yield as a result of the zero kerf in combination with the increased bending strength of the diced dies (no chipping or micro cracks occur).
  • Higher throughput by the unrivalled dicing speed (up to 300 mm/s) for thin wafers (50 ... 250 µm).
  • Reduced cost of ownership because of the ablation free process – neither protection or cleaning steps nor consumables are required.
  • The excellent edge quality in combination with other advances can be used for new and improved products like power devices, MEMS, optical devices or RFID.

Edwards
iXH series of vacuum pumps

Semiconductor manufacturing processes, such as atomic layer deposition (ALD), and compound semiconductor processes, such as gallium nitride, are creating challenges for vacuum pump technology in terms of powder handling, hydrogen flow, fluorine plasma cleans, ammonia flows and pre cursor reactions.


Click here to view

The iXH has been specifically designed to meet these challenges with enhanced purge flow, temperature-controlled operating range, light gas performance and corrosive gas resistance. Its extended capabilities also promise improved CoO by lengthening pump life and helping to deliver lower utility costs.”

According to Edwards, ALD processes typically deposit less than 10% of the pre curser on the wafer, thus increasing the potential for deposition in the pump. To manage such challenging conditions, the iXH offers improved thermal control and increased torque. With its larger exhaust stages and the Gas Buster inlet purge, the iXH is also designed to deal with extreme powder processes with TEOS flows above 5 g/min.

For manufacturing compound semiconductors, such as those based on gallium nitride, where large flows of hydrogen and ammonia are required, the iXH pump mechanism has been optimised to handle hydrogen and to better withstand the corrosive effects of ammonia.

The iXH also features Active Utility Control (AUC), which includes an idle mode for periods when the pump is not in use. This can reduce utility costs by more than 10% compared to the previous generation of Edwards’s harsh process pumps.

An additional feature is its modular design.

Entegris
Torrento High-Flow Liquid Filters


Click here to view

Product Outline: Entegris’ Torrento family of high-flow liquid filters help improve liquid contamination control of nano-scale particles in wet etch and clean (WEC) manufacturing processes used in advanced semiconductor applications. Built on a combination of new membrane technology and an advanced ATE device construction, the Torrento filters provide high-yield, rapid bath clean-up cycles, extended filter life, allow for fast changeouts and increase cleanliness.

Problem: As semiconductor manufacturers drive their sub-45nm technology applications, contamination control becomes increasingly more difficult. The filter retention is extremely critical as the purity of the chemicals used in WEC can directly correlate to wafer yields. To remove increasingly smaller contamination particles, wafer fabricators found themselves using filters with smaller pores, which forced reduced filter flow and ultimately slowed wafer processing speed.

Solution: With the Torrento high-flux platform of WEC filters, semiconductor manufacturers can maintain ultra-high flow rates without sacrificing chemical purity at the 20nm rating. That’s because the Torrento 20nm filters use a specialized nondewetting Teflon membrane technology. Torrento filters also have a larger surface area than general use filters due to an advanced ATE device construction technology.

The combined effect is a filter that allows manufacturers to reduce particle-related wafer defects, decrease process cycle time, and increase filter life. The low filter resistance also is designed to reduce pump strokes and decrease wear and tear.

Applications: The capability to maintain flow rate at an extremely small pore size in outgassing chemistries such as SPM, SC1 and SC2 ensures the stable processing conditions needed for the high CpK results demanded at advanced technology nodes.

Platform: Torrento filters are available in cartridge and disposable formats to accommodate installation flexibility and upgrades. The disposable filter eliminates operator handling of the filter element, further minimizing contamination risk. The disposable design also reduces the potential operator exposure to chemicals during installation and disposal.

For Additional Information:
Jessica Eull
Padilla Speer Beardsley
612.455.1792
jeull@psbpr.com

MASER Engineering
Fast board level interconnect test service


Click here to view

MASER Engineering has extended its test and diagnostic services with a tool for board level interconnect tests.

Modern Chip Scale and Ball Grid array packages are the most common package style for Integrated Circuits in consumer handheld equipment. The introduction of lead-free solder interconnects have resulted in a change in the contact reliability. The long history of leaded interconnects had to be replaced by new models of the failure mechanism and test data.

The first test results were also used to adjust the metallurgical properties and the assembly process. To have fast feedback, new test methods have been developed too. In addition to the conventional stress test, based on slow and fast temperature cycling tests, new techniques and systems were introduced for even faster accelerated stress tests.

A major player in hand held applications defined a bouncing drop test with a new designed drop test system. This test method uses continuously monitored daisy-chain devices and glitch detection during the 1500g shock impact. The drop test system has a specific construction to allow multiple drop endurance testing in a reasonable time.

MASER Engineering has made this test capability available to customers in order to evaluate the robustness of the SMD solder interconnect system of the chosen package. MASER Engineering demonstrated further impact on contact reliability due to the introduction of low-K oxides in sub 100nm technology devices. Thanks to the fast accelerated test method, this effect could be examined before the market introduction, thus saving big field return costs.

This tool for fast board level bending tests is added to the range of systems for mechanical stress test of solder interconnects. The core of the system is a precision sine movement of a two point bending tool. The daisy-chain devices are mounted on a mobile phone simulating PCB and connected to a resistor scanner system. The test board is supported at the two edges and pushed down at two points with a defined distance. The bending amplitude results a lateral mechanical force on the metal interconnections. The new system is able to maintain precision bending at 5 Hz for large amount of bending movements. The system can be programmed to bend until a specific failure mode in one or all devices on the PCB. A detailed failure analysis and SEM/EDX inspection will show the defect properties in the intermetallic layer that has cracked. Both the mechanical drop test and bending systems and the F/A tools are available to component suppliers and OEM companies that require detailed reliability data on their connection technology.

The Awards Team

 

David Ridsdale
Editor In Chief
dr@angelbcl.co.uk

Jackie Cannon
Publisher
jc@angelbcl.co.uk
     
 
Stephen Whitehurst
Commercial Director
stephen@angelbc.co.uk
Tommy Beazley
Account Manager
tb@angelbcl.co.uk
     
   
Shehzad Munshi
Account Manager
sm@angelbcl.co.uk
   
     
     
 
Tom Brun
USA Account Manager
tbrun@brunmedia.com
 
Janice Jenkins
USA Account Manager
jjenkins@brunmedia.com
 
2008 Winners

The committee had in excess of 120 nominations from
vendor, manufacturers and users. Congratulations to
all the companies that made the shortlist

 

Click here to view the Awards Winners Gallery 2008


Some of the Shortlisted Companies in 2009
Our Supporters

 

 
 
MicroNanoSystems
 
Semiconductor India
 
 
 
 
EuroAsia Semiconductor Home Semiconductor India MicroNanoSystems EuroAsia IC Industry Awards EuroAsia Directory Home Terms & Conditions Privacy Policy Contact Us