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Blaze DFM qualified by STARC for 65nm leakage power optimization
Blaze DFM has been chosen by the Semiconductor Technology Academic Research Centre (STARC) to provide leakage power optimization software that will be integrated into the STARCAD-CEL (Certified Engineering Linkage, one step ahead of DFM) reference design methodology.
Blaze DFM has been chosen by the Semiconductor Technology Academic Research Centre (STARC) to provide leakage power optimization software that will be integrated into the STARCAD-CEL (Certified Engineering Linkage, one step ahead of DFM) reference design methodology. With this methodology, STARC - a Japanese semiconductor technology research organization supported by Japanese IDMs - is targeting the establishment of a process-friendly and low-power reference flow that strives to eliminate manufacturing uncertainty in 45nm-32nm system LSI designs.As part of the qualification process, STARC performed a detailed evaluation of the Blaze MO leakage optimization solution using a three million gate, 65nm chip. Blaze MO employs two complementary techniques for leakage power reduction – transistor gate length biasing and threshold voltage (Vt) assignment. First, they created a baseline design using their standard STARCAD-CEL design methodology. Then, they optimized the design using Blaze MO's patented gate length biasing capability. Subthreshold leakage power in the Blaze-optimized design was 45% lower than in the baseline design. Next, they re-optimized the design with Blaze MO for both leakage power and timing using gate length biasing and Vt assignment with multi-Vt libraries. Leakage power was 36% lower and timing was 30% faster than the original baseline design."For many of our member companies, power has become the most critical yield-limiting factor for their designs," said Nobuyuki Nishiguchi, vice-president and general manager at STARC. "A reduction in leakage power of this magnitude, in addition to what is already achievable using more conventional techniques, adds significant value to any design flow for 65nm or below.""STARC's endorsement of Blaze MO is of great strategic importance because all of the member companies will be presented with the results of their evaluation," said Jacob Jacobsson, president and CEO at Blaze. "STARC plays a key role in identifying and qualifying new technologies for their consortium members and we're looking forward to working with them to address the critical design challenges at 65nm and below."
TSMC versus GlobalFoundries: Semiconductor Design Enablement!
As mentioned in previous blogs, design enablement is a key enabler to fabless semiconductor design and manufacture, without question. The purpose of this blog (in 500 words) is to compare and contrast two very different design enablement strategies and engage the semiconductor community in a meaningful discussion.